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| 型號(hào)： | AD9992BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數(shù)： | 51/92頁 |
| 文件大小： | 718K |
| 代理商： | AD9992BBCZRL |
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AD9992
GENERAL-PURPOSE OUTPUTS (GPO
S
)
The AD9992 provides programmable outputs to control a
mechanical shutter, strobe/flash, the CCD bias select signal, or
any other external component with general-purpose (GP)
signals. Eight GP signals, with up to four toggles each, are
available that can be programmed and assigned to special GPO
pins. These pins are bidirectional and allow visibility (as an
output) and external control (as an input) of HBLK, PBLK,
CLPOB, and OUTCONTROL. The registers introduced in this
section are described in Table 22.
Rev. 0 | Page 51 of 92
GP Toggles
When configured as an output, each GPO1 to GPO8 output can
positions. The GP signals are independent and can be linked to
either a specific VD period or over a range of VD periods via
the primary or secondary field counters through the GP
protocol register (Address 0x73). As a result of their
associations with the field counters, the GP toggles inherit the
characteristics of the field counters, such as RapidShot and
ShotDelay. To use the GP toggles
1.
Program the toggle positions (Address 0x7A to
Address 0xA9).
2.
Program the protocol (Address 0x73).
3.
Program the counter parameters (Address 0x71 to
Address 0x72).
4.
Activate the counter (Address 0x70).
Table 22. GPO Registers
Register
Length
GP1_PROTOCOL
3b
GP2_PROTOCOL
3b
GP3_PROTOCOL
3b
GP4_PROTOCOL
3b
GP5_PROTOCOL
3b
GP6_PROTOCOL
3b
GP7_PROTOCOL
3b
GP8_PROTOCOL
8b
MANUAL_TRIG
8b
GP<1:8>_POL
8b
SEL_GP<1:8>
8b
For Protocol 1 (no counter association), skip Steps 3 and 4.
With these four steps, the GP signals can be programmed to
accomplish many common tasks. Careful protocol selection and
application of the field counters yields efficient results to allow
the GP signals smooth integration with concurrent operations.
Note that the SUBCK and VSG masks are linked to the primary
counter; however, if their parameters are 0, the GPO can use the
primary counter without expose/read activity.
The secondary counter is independent and can be used
simultaneously with the primary counter. Some applications
may require the use of both primary and secondary field
counters with different GPO protocols, start times, and
durations. Such operations are easily handled by the AD9992.
Several simple examples of GPO applications using only one
GPO and one field counter follow. These examples can be used
as building blocks for more complex GPO activity. In addition,
specific GPO signals can be passed through a 4-input LUT to
realize combinational logic between them. For example, GP1
and GP2 can be sent through an XOR look-up table, and the
result can be delivered on GP1, GP2, or both. Also, either GP1
or GP2 can deliver their original toggles.
Range
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
Off/on
Low/high
Off/on
Description
0: idle.
1: no counter association, use MANUAL_TRIG bits to enable each GP signal.
2: link to primary counter.
3: link to secondary counter.
4: link to mode counter (from vertical timing generation).
5: primary repeat (allows GP signals to repeat with RapidShot).
6: secondary repeat (allows GP signals to repeat with RapidShot).
7: keep on.
Manual trigger for each GP signal, for use with Protocol 1.
Starting polarity for GP signals, only updated during PROTOCOL = 0.
1: select GP toggles visible at GPO1 to GPO8 when output is enabled (default);
0: select vertical signals visible at GPO4 to GPO8 when output is enabled.
GPO4: SUBCK.
GPO5: XV21.
GPO6: XV22.
GPO7: XV23.
GPO8: XV24.
1: enable GPO1 to GPO8 outputs (one bit per output);
0: disable GPO1 to GPO8 outputs, pins will be high-Z state (default).
Send GP signals through a programmable look-up table (LUT).
Desired logic to be realized on GP1 combined with GP2.
Desired logic to be realized on GP3 combined with GP4.
GPO_OUTPUT_EN
8b
Off/on
GP*_USE_LUT
LUT_FOR_GP12
LUT_FOR_GP34
8b
4b
4b
Off/on
Logic setting
Logic setting
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| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1 |
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| AD9994 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
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