參數(shù)資料
型號(hào): AD9992BBCZRL
廠商: ANALOG DEVICES INC
元件分類: 消費(fèi)家電
英文描述: 12-Bit CCD Signal Processor with Precision Timing Generator
中文描述: SPECIALTY CONSUMER CIRCUIT, PBGA105
封裝: 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105
文件頁數(shù): 27/92頁
文件大?。?/td> 718K
代理商: AD9992BBCZRL
AD9992
Rev. 0 | Page 27 of 92
REGIREGIREGION 0: USE V-SEQUENCE 3
REGION 1: USE V-SEQUENCE 2
REGION 2: USE V-SEQUENCE 1
REGIREGION 0: USE V-SEQUENCE 3
REGION 2: USE V-SEQUENCE 1
REGION 0: USE V-SEQUENCE 2
REGION 3: USE V-SEQUENCE 0
REGION 4: USE V-SEQUENCE 2
V1
V2
V23
V24
V1
V2
V3
FIELD 0
FIELD1
FIELD2
FIELD0
FIELD1
FIELD2
FIELD3
FIELD4
FIELD5
FIELD1
FIELD4
FIELD2
V3
V23
V24
VPAT0
V1
V2
V23
V24
V3
V1
V2
V23
V24
V3
V1
V2
V23
V24
V3
VPAT1
1
2
3
4
CREATE THE VERTICAL PATTERN GROUPS,
UP TO FOUR TOGGLE POSITIONS FOR EACH OUTPUT.
BUILD THE V-SEQUENCES BY ADDING START POLARITY,
LINE START POSITION, NUMBER OF REPEATS, ALTERNATION,
GROUP A/B/C/D INFORMATION, AND HBLK/CLPOB PULSES.
V-SEQUENCE 0
(VPAT0, 1 REP)
V-SEQUENCE 1
(VPAT1, 2 REP)
V-SEQUENCE 2
(VPAT1, N REP)
BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS
AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH
(MAXIMUM OF NINE REGIONS IN EACH FIELD).
USE THE MODE REGISTERS TO CONTROL WHICH FIELDS
ARE USED, AND IN WHAT ORDER (MAXIMUM OF SEVEN
FIELDS MAY BE COMBINED IN ANY ORDER).
0
Figure 32. Summary of Vertical Timing Generation
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