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參數(shù)資料
| 型號(hào)： | AD9992BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數(shù)： | 39/92頁 |
| 文件大?。?/td> | 718K |
| 代理商： | AD9992BBCZRL |
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AD9992
Complete Field: Combining V-Sequences
After the V-sequences are created, they are combined to create
different readout fields. A field consists of up to nine regions,
and within each region, a different V-sequence can be selected.
Figure 47 shows how the sequence change positions (SCP)
designate the line boundary for each region and how the SEQ
registers then select which V-sequence is used in each region.
Registers to control the VSG outputs are also included in the
field registers. Table 16 summarizes the registers used to create
the different fields.
Rev. 0 | Page 39 of 92
The SEQ registers, one for each region, select which of the
V-sequences are active in each region. The MULT_SWEEP
registers, one for each region, are used to enable sweep mode
and/or multiplier mode in any region. The SCP registers create
the line boundaries for each region. The VDLEN register
specifies the total number of lines in the field. The HDLEN
registers specifies the total number of pixels per line, and the
HDLASTLEN register specifies the number of pixels in the last
line of the field. The VPATSECOND register is used to add a
second V-pattern group to the V1 to V10 outputs in the vertical
sensor gate (VSG) line.
The SGMASK register is used to enable or disable each individual
VSG output. There are two bits for each VSG output to enable
separate masking in SGACTLINE1 and SGACTLINE2.
Setting a masking bit high masks the output; setting it low
enables the output. The VSGPATSEL register assigns one of the
eight SG patterns to each VSG output. The individual SG
patterns are created separately using the SG pattern registers.
The SGACTLINE1 register specifies which line in the field
contains the VSG outputs. The optional SGACTLINE2 register
allows the same VSG pulses to be repeated on a different line.
Separate masking is not available for SGACTLINE1 and
SGACTLINE2.
Table 16. Field Registers (CLPOB, PBLK Masking Shown in Table 9)
Register
Length
Range
SEQx
5b
0 to 31 V-sequence no.
MULT_SWEEP
2b
0 to 3
SCP
13b
0 to 8191 line no.
VDLEN
13b
0 to 8191 lines
HDLASTLEN
13b
0 to 8191 pixels
VSGPATSEL
24b
High/low
Description
Selected V-sequence for each region in the field.
Enables multiplier mode and/or sweep mode for each region.
0: multiplier off, sweep off.
1: multiplier off, sweep on.
2: multiplier on, sweep off.
3: multiplier on, sweep on.
Sequence change position for each region.
Total number of lines in each field.
Length in pixels of the last HD line in each field.
VSGPATSEL selects which V-pattern toggle positions are used. When set to 0,
Toggle 1 and Toggle 2 are used. When set to 1, Toggle 3 and Toggle 4 are used.
[0]: XV1 selection (0 = use TOG1, TOG2; 1 = use TOG3, TOG4).
…
[23]: XV24 selection.
Set high to mask each individual VSG output.
[0]: XV1 mask.
…
[23]: XV24 mask.
Selects the line in the field where the VSG signals are active.
Selects a second line in the field to repeat the VSG signals. If not used,
set this equal to SGACTLINE1 or to the maximum value.
SGMASK
SGACTLINE1
SGACTLINE2
24b
13b
13b
High/low, each VSG
0 to 8191 line no.
0 to 8191 line no.
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