- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373973 > AD9992BBCZRL (ANALOG DEVICES INC) 12-Bit CCD Signal Processor with Precision Timing Generator PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9992BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數(shù)： | 40/92頁 |
| 文件大?。?/td> | 718K |
| 代理商： | AD9992BBCZRL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當(dāng)前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
AD9992
Rev. 0 | Page 40 of 92
VD
REGION 0
FIELD SETTINGS:
1. SEQUENCE CHANGE POSITIONS (SCP0 TO SCP8) DEFINE EACH OF THE NINE AVAILABLE REGIONS IN THE FIELD.
2. SEQ0 TO SEQ8 SELECT THE DESIRED V-SEQUENCE FOR EACH REGION.
3. SGACTLINE1 REGISTER SELECTS WHICH HD LINE IN THE FIELD CONTAINS THE SENSOR GATE PULSE(S).
V1 TO VN
HD
SCP1
SCP2
SEQ0
SEQ1
SCP3
SEQ2
SCP4
SEQ3
SCP5
SEQ4
SCP8
SEQ8
REGION 1
REGION 2
REGION 3
REGION 4
REGION 8
VSG
SGACTLINE1
SCP0
0
Figure 47. Complete Field is Divided into Regions
VD
V1 TO VN
HD
REGION 1: SWEEP REGION
LINE 0
LINE 1
REGION 0
REGION 2
LINE 24
LINE 25
LINE 2
SCP1
SCP2
0
Figure 48. Example of Sweep Region for High Speed Vertical Shift
Sweep Mode Operation
The AD9992 contains an additional mode of vertical timing
operation called sweep mode. This mode is used to generate a
large number of repetitive pulses that span across multiple HD
lines. An example of where this mode is needed is at the start of
the CCD readout operation. At the end of the image exposure
before the image is transferred by the sensor gate pulses, the
vertical interline CCD registers should be free of all charge. This
can be accomplished by quickly shifting out any charge using a
long series of pulses from the vertical outputs. Depending on
the vertical resolution of the CCD, up to 3000 clock cycles
might be needed to shift the charge out of each vertical CCD
line. This operation spans across multiple HD line lengths.
Normally, the AD9992 vertical timing must be contained within
one HD line length, but when sweep mode is enabled, the HD
boundaries are ignored until the region is finished. To enable
sweep mode within any region, program the appropriate SWEEP
register to high.
Figure 48 shows an example of the sweep mode operation. The
number of vertical pulses needed depends on the vertical reso-
lution of the CCD. The toggle positions for the V1 to V24 signals
are generated using the V-pattern registers (shown in Table 12).
A single pulse is created using the polarity and toggle position
registers. The number of repetitions is then programmed to match
the number of vertical shifts required by the CCD. Repetitions
are programmed into the V-sequence registers (shown in
Table 13) by using the VREP registers. This produces a pulse
train of the appropriate length. Normally, the pulse train is
truncated at the end of the HD line length, but when sweep
mode is enabled for this region, the HD boundaries are ignored.
In Figure 48, the sweep region occupies 23 HD lines. After the
sweep mode region is complete, normal sequence operation
resumes in the next region. When using sweep mode, be sure to
set the region boundaries (using the sequence change positions)
to the appropriate lines to prevent the sweep operation from
overlapping the next V-sequence.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9995KCP | 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator |
| AD9995KCPRL | 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator |
| AD9995 | 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator |
| ADA4000-2ARMZ-RL | Low Cost, Precision JFET Input Operational Amplifiers |
| ADA4000-1 | Low Cost, Precision JFET Input Operational Amplifiers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1,500 |
| AD9993-EBZ | 功能描述:EVAL BOARD MXFE AD9993 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1 |
| AD9994 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9994BCP | 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 12-BIT 64LFCSP - Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。