參數(shù)資料
型號： AD9992BBCZRL
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： 12-Bit CCD Signal Processor with Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA105
封裝： 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105
文件頁數(shù)： 13/92頁
文件大小： 718K
代理商： AD9992BBCZRL
AD9992
SYSTEM OVERVIEW
Figure 11 shows the typical system block diagram for the AD9992
in master mode. The CCD output is processed by the AD9992’s
AFE circuitry, which consists of a CDS, VGA, black level clamp,
and ADC. The digitized pixel information is sent to the digital
image processor chip, which performs the postprocessing and
compression. To operate the CCD, all CCD timing parameters
are programmed into the AD9992 from the system microprocessor
through the 3-wire serial interface. From the master clock, CLI,
provided by the image processor or external crystal, the AD9992
generates the CCD’s horizontal and vertical clocks and internal
AFE clocks. External synchronization is provided by a sync
pulse from the microprocessor, which resets the internal
counters and resyncs the VD and HD outputs.
Rev. 0 | Page 13 of 92
CCDIN
GPO1 TO GPO8
H1 TO H8, HL,
RG, VSUB
XV1 TO XV24, SUBCK
CCD
AD9992
AFETG
DIGITAL
IMAGE
PROCESSING
ASIC
DOUT
DCLK
HD, VD
CLI
SERIAL
INTERFACE
SYNC
μP
V-DRIVER
0
Figure 11. Typical System Block Diagram, Master Mode
Alternatively, the AD9992 can be operated in slave mode. In
this mode, the VD and HD are provided externally from the
image processor, and all AD9992 timing is synchronized with
VD and HD.
The H-drivers for H1 to H8, HL, and RG are included in the
AD9992, allowing these clocks to be directly connected to the
CCD. An H-driver voltage of up to 3.3 V is supported. An
external V-driver is required for the vertical transfer clocks, the
sensor gate pulses, and the substrate clock.
The AD9992 includes programmable general-purpose outputs
(GPO), which can trigger mechanical shutter and strobe (flash)
circuitry.
Figure 12 and Figure 13 show the maximum horizontal and
vertical counter dimensions for the AD9992. All internal
horizontal and vertical clocking is controlled by these counters,
which specify line and pixel locations. Maximum HD length is
8192 pixels per line, and maximum VD length is 8192 lines per
field.
13-BIT HORIZONTAL = 8192 PIXELS MAX
13-BIT VERTICAL = 8192 LINES MAX
MAXIMUM COUNTER DIMENSIONS
0
Figure 12. Vertical and Horizontal Counters
VD
HD
MAX VD LENGTH IS 8192 LINES
CLI
MAX HD LENGTH IS 8192 PIXELS
0
Figure 13. Maximum VD/HD Dimensions
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相關代理商/技術參數(shù)
參數(shù)描述
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