參數(shù)資料
型號: 56F8014
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 81/124頁
文件大?。?/td> 1878K
代理商: 56F8014
Interrupts
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
81
Figure 6-16 Timing Relationships of Reset Signal to Clocks
6.8 Interrupts
The SIM generates no interrupts.
RST
MSTR_OSC
CKGEN_RST
SYS_CLK_x2
SYS_CLK
SYS_CLK_D
SYS_CLK_DIV2
PERIP_RST
CORE_RST
Switch on falling OSC_CLK
96 MSTR_OSC cycles
Switch on falling SYS_CLK
32 SYS_CLK cycles delay
32 SYS_CLK cycles delay
Maximum Delay = 64 MSTR_OSC cycles for POR reset extension and 32 MSTR_OSC cycles
for combined reset extension
Switch on falling SYS_CLK
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