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參數(shù)資料
| 型號(hào)： | 56F8014 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號(hào)控制器 |
| 文件頁(yè)數(shù)： | 77/124頁(yè) |
| 文件大?。?/td> | 1878K |
| 代理商： | 56F8014 |
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Power-Down Modes
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
77
6.5 Power-Down Modes
The 56F8014 operates in one of five Power-Down modes, as shown in
Table 6-3
.
The power modes provide additional means to disable clock domains, configure the voltage regulator, and
configure clock generation to manage power utilization, as shown in
Table 6-3
. Run, Wait, and Stop
modes provide means of enabling/disabling the peripheral and/or core clocking as a group. Stop disable
controls are provided for selected peripherals in the control register (SCI and TMR channels) so that these
peripheral clocks can optionally continue to operate in Stop mode and generate interrupts which will return
the part from Stop to Run mode. Standby mode provides normal operation but at very low speed and power
Table 6-3 Clock Operation in Power-Down Modes
Mode
Core Clocks
Peripheral Clocks
Description
Run
Core and memory
clocks disabled
Peripheral clocks
enabled
Device is fully functional
Wait
Core and memory
clocks disabled
Peripheral clocks
enabled
Core executes WAIT instruction to enter this
mode.
Typically used for power-conscious applications.
Possible recoveries from Wait mode to Run
mode are:
1. Any interrupt
2. Executing a Debug mode entry command
during the 56800E core JTAG interface
2. Any reset (POR, external, software, COP)
Stop
Master clock generation in the OCCS
remains operational, but the SIM disables
the generation of system and peripheral
clocks.
Core executes STOP instruction to enter this
mode. Possible recoveries from Stop mode to
Run mode are:
1. Interrupt from TMR channels that have been
configured to operate in Stop mode (TCx_SD)
2. Interrupt for SCI configured to operate in Stop
mode (SCI_SD)
3. Low-voltage interrupt
4. Executing a Debug mode entry command
using the 56800E core JTAG interface
5. Any reset (POR, external, software, COP)
Standby
The OCCS generates the SYS_CLK_x2
clock at a reduced frequency (400kHz). The
PLL and HS_PERF clocks are disabled and
the high-speed peripheral option is not
available. System and peripheral clocks
operate at 200kHz.
The user configures the OCCS and SIM to select
the relaxation oscillator clock source (PRECS),
shut down the PLL (PLLPD), put the relaxation
oscillator in Standby mode (ROSB), and put the
large regulator in Standby (LRSTDBY). The part
is fully operational, but operating at a minimum
frequency and power configuration. Recovery
requires reversing the sequence used to enter
this mode (allowing for PLL lock time).
Power-Down
Master clock generation in the OCCS is
completely shut down. All system and
peripheral clocks are disabled.
The user configures the OCCS and SIM to enter
Standby mode as shown in the previous
description, followed by powering down the
oscillator (ROPD). The only possible recoveries
from this mode are:
1. External reset
2. Power-on reset
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