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參數(shù)資料
| 型號(hào)： | 56F8014 |
| 廠(chǎng)商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號(hào)控制器 |
| 文件頁(yè)數(shù)： | 110/124頁(yè) |
| 文件大?。?/td> | 1878K |
| 代理商： | 56F8014 |
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56F8014 Technical Data, Rev. 3
110
Freescale Semiconductor
Preliminary
10.15 Equivalent Circuit for ADC Inputs
Figure 10-17
illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed
at the same time that S3 is closed/open. When S1/S2 are closed & S3 is open, one input of the sample and
hold circuit moves to (V
REFH
-V
REFL
)/2, while the other charges to the analog input voltage. When the
switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about (V
REFH
-V
REFL
)/2. The switches switch
on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that there
are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into
the S/H output voltage, as S1 provides isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog input
voltage, V
REF
and the ADC clock frequency.
Offset Voltage Internal Ref
V
OFFSET
—
+/- 8
+/- 15
mV
Gain Error (transfer gain)
E
GAIN
.99
1
1.01
—
Offset Voltage External Ref
V
OFFSET
—
+/- 3
TBD
mV
Signal-to-noise ratio
SNR
TBD
62 to 65.7
dB
Total Harmonic Distortion
THD
TBD
63 to 68
dB
Spurious Free Dynamic Range
SFDR
TBD
67 to 70.3
dB
Signal-to-noise plus distortion
SINAD
TBD
61 to 63.9
dB
Effective Number Of Bits
ENOB
9.1
9.6 to 10.4
Bits
1. All measurements were made at V
DD
= 3.3V, V
REFH
= 3.3V, and V
REFL
= ground
2. INL measured from V
IN
= V
REFL
to V
IN
= V
REFH
3. LSB = Least Significant Bit
4. INL measure from V
IN
= 0.1 V
REFH
to V
IN
= 0.9V
REFH
5. Includes power-up of ADC and V
REF
6. ADC clock cycles
7. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance
of the ADC.
Table 10-19 ADC Parameters
1
(Continued)
Characteristic
Symbol
Min
Typ
Max
Unit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 56F8014_07 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| 56F8014_08 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| 56F801E | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| 56F801XBLUG | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| 56F802 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
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