參數(shù)資料
型號(hào): 56F8014
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù): 59/124頁(yè)
文件大?。?/td> 1878K
代理商: 56F8014
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Register Descriptions
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
59
5.6.15.1 IRQ Pending (PENDING)—Bits 45–33
This register combines with IRQP0 and IRQP1 to represent the pending IRQs for interrupt vector numbers
2 through 45.
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.16
Interrupt Control Register (ICTRL)
Figure 5-18 Interrupt Control Register (ICTRL)
5.6.16.1 Interrupt (INT)—Bit 15
This
read-only
bit reflects the state of the interrupt to the 56800E core.
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
5.6.16.2 Interrupt Priority Level (IPIC)—Bits 14–13
These
read-only
bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being
sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service
routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
$Base + $12
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
RESET
INT
IPIC
VAB
INT_
DIS
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
Table 5-3 Interrupt Priority Encoding
IPIC_VALUE[1:0]
Current Interrupt
Priority Level
Required Nested
Exception Priority
00
No interrupt or SWILP
Priorities 0, 1, 2, 3
01
Priority 0
Priorities 1, 2, 3
10
Priority 1
Priorities 2, 3
11
Priority 2 or 3
Priority 3
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