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參數資料
| 型號： | 56F8014 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數字信號控制器 |
| 文件頁數： | 69/124頁 |
| 文件大?。?/td> | 1878K |
| 代理商： | 56F8014 |
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Register Descriptions
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
69
6.3.7
The CLKO select register can be used to multiplex out selected clocks generated inside the clock
generation and SIM modules. All functionality is for test purposes only and is subject to
unspecified latencies. Glitches may be produced when the clock is enabled or switched.
CLKO Select Register (SIM_CLKOUT)
The lower four bits of the GPIO A register can function as GPIO, PWM, or as additional clock output
signals. GPIO has priority and is enabled/disabled via the GPIOA_PEREN. If GPIOA[3:0] are
programmed to operate as peripheral outputs, then the choice between PWM and additional clock outputs
is done here in the CLKOUT. The default state is for the peripheral function of GPIOA[3:0] to be
programmed as PWM. This can be changed by altering PWM3 through PWM0.
Figure 6-8 CLKO Select Register (SIM_CLKOUT)
6.3.7.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bits 15–10
6.3.7.2
PWM3—Bit 9
0 = Peripheral output function of GPIOA[3] is defined to be PWM3
1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock
6.3.7.3
PWM2—Bit 8
0 = Peripheral output function of GPIOA[2] is defined to be PWM2
1 = Peripheral output function of GPIOA[2] is defined to be the system clock
6.3.7.4
PWM1—Bit 7
0 = Peripheral output function of GPIOA[1] is defined to be PWM1
1 = Peripheral output function of GPIOA[1] is defined to be two times the rate of the system clock
6.3.7.5
PWM0—Bit 6
0 = Peripheral output function of GPIOA[0] is defined to be PWM0
1 = Peripheral output function of GPIOA[0] is defined to be three times the rate of the system clock
6.3.7.6
Clockout Disable (CLKDIS)—Bit 5
0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL
1 = CLKOUT is 0
Base + $A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
RESET
0
0
0
0
0
0
PWM
3
PWM
2
PWM1
PWM0
CLK
DIS
CLKOSEL
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
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相關代理商/技術參數 |
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