參數(shù)資料
型號: 56F8014
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 19/124頁
文件大小: 1878K
代理商: 56F8014
56F8014 Signal Pins
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
19
TDO
(GPIOD1)
31
Output
Input/
Output
Tri-stated,
pulled high
internally
Test Data Output
— This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
Port D GPIO
— This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TDO.
GPIOB0
(SCLK)
(SCL
3
)
21
Input/
Output
Input/
Output
Input/
Output
Input, pulled
high
internally
Port B GPIO
— This GPIO pin can be individually programmed as
an input or output pin.
SPI Serial Clock
— In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input. A Schmitt trigger input is used for noise
immunity.
Serial Data
— This pin serves as the I
2
C serial clock.
After reset, the default state is GPIOB0. The peripheral functionality
is controlled via the SIM. See
Section 6.3.8
.
3.
This signal is also brought out on the GPIOB7 pin.
GPIOB1
(SS)
(SDA
4
)
1
Input/
Output
Input
Input/
Output
Input, pulled
high
internally
Port B GPIO
— This GPIO pin can be individually programmed as
an input or output pin.
SPI Slave Select
— SS is used in slave mode to indicate to the SPI
module that the current transfer is to be received.
Serial Clock
— This pin serves as the I
2
C serial data line.
After reset, the default state is GPIOB1. The peripheral functionality
is controlled via the SIM. See
Section 6.3.8
.
4.
This signal is also brought out on the GPIOB6 pin.
Return to
Table 2-2
Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
Type
State During
Reset
Signal Description
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