參數(shù)資料
型號(hào): 56F8014
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁數(shù): 17/124頁
文件大?。?/td> 1878K
代理商: 56F8014
56F8014 Signal Pins
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
17
GPIOB7
(TXD)
(SCL
2
)
2
Input/
Output
Input/
Output
Input/
Output
Input, pulled
high
internally
Port B GPIO
— This GPIO pin can be individually programmed as
an input or output pin.
Transmit Data
— SCI transmit data output or transmit / receive in
single wire opeation.
Serial Clock
— This pin serves as the I
2
C serial clock.
After reset, the default state is GPIOB7. The peripheral functionality
is controlled via the SIM. See
Section 6.3.8
.
2.
This signal is also brought out on the GPIOB0 pin.
RESET
(GPIOA7)
16
Input
Input/Open
Drain
Output
Input, pulled
high
internally
Reset
— This input is a direct hardware reset on the processor.
When RESET is asserted low, the chip is initialized and placed in the
reset state. A Schmitt trigger input is used for noise immunity. The
internal reset signal will be deasserted synchronous with the internal
clocks after a fixed number of internal clocks.
Port A GPIO
— This GPIO pin can be individually programmed as
an input or open drain output pin. Note that RESET functionality is
disabled in this mode and the chip can only be reset via POR, COP
reset, or software reset.
After reset, the default state is RESET.
GPIOB4
(T0)
(CLKO)
19
Input/
Output
Input/
Output
Output
Input, pulled
high
internally
Port B GPIO
— This GPIO pin can be individually programmed as
an input or output pin.
T0
— Timer, Channel 0
Clock Output
— This is a buffered clock signal. Using the
SIM_CLKO Select Register (SIM_CLKOSR), this pin can be
programmed as any of the following: disabled (logic 0), CLK_MSTR
(system clock), IPBus clock, or oscillator output. See
Section 6.3.7
.
After reset, the default state is GPIOB4. The peripheral functionality
is controlled via the SIM. See
Section 6.3.8
.
Return to
Table 2-2
Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
Type
State During
Reset
Signal Description
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