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Electrical Design Considerations
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
121
Module
Register Name
Peripheral Reference Manual
Data Sheet
Processor
Expert
Acronym
Memory Address
New Acronym
Legacy
Acronym
New Acronym
Legacy Acronym
Start
End
FM
Clock Divider Register
Configuration Register
Security High Half Register
Security Low Half Register
Protection Register
User Status Register
Command Register
Address Register
Data Buffer Register
Optional Data 1 Register
Test Array Signature Register
CLKDIV
CNFG
SECHI
SECLO
PROT
USTAT
CMD
ADDR
DATA
OPT1
TSTSIG
FMCLKD
FMCR
FMSECH
FMSECL
FMPROT
FMUSTAT
FMCMD
FMADDR
FMDATA
FMOPT1
FMTST_SIG
FM_CLKDIV
FM_CNFG
FM_SECHI
FM_SECLO
FM_PROT
FM_USTAT
FM_CMD
FM_ADDR
FM_DATA
FM_OPT1
FM_TSTSIG
FMCLKD
FMCR
FMSECH
FMSECL
FMPROT
FMUSTAT
FMCMD
FMADDR
FMDATA
FMOPT1
FMTST_SIG
FMCLKD
FMCR
FMSECH
FMSECL
FMPROT
FMUSTAT
FMCMD
0xF400
0xF401
0xF403
0xF404
0xF410
0xF413
0xF414
0xF416
0xF418
0xF41B
0xF41D
FMOPT1
x
= A (
n
=0) B (
n
=1) C (
n
=2) D (
n
=3)
GPIO_
x
_PUR
GPIO_
x
_DR
GPIO_
x
_DDR
GPIO_
x
_PER
GPIO_
x
_IAR
GPIO_
x
_IENR
GPIO_
x
_IPOLR
GPIO_
x
_IPR
GPIO_
x
_IESR
GPIO_
x
_PPMODE
GPIO_
x
_RAWDATA
GPIO_
x
_DRIVE
GPIO
Pull-Up Enable Register
Data Register
Data Direction Register
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
Interrupt Edge Polarity Register
Interrupt Pending Register
Interrupt Edge Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Register
Drive Strength Control Register
PUPEN
DATA
DDIR
PEREN
IASSRT
IEN
IEPOL
IPEND
IEDGE
PPOUTM
RDATA
DRIVE
PUR
DR
DDR
PER
IAR
IENR
IPOLR
IPR
IESR
PPMODE
RAWDATA
DRIVE
GPIO
x
_PUPEN
GPIO
x
_DATA
GPIO
x
_DDIR
GPIO
x
_PEREN
GPIO
x
_IASSRT
GPIO
x
_IEN
GPIO
x
_IEPOL
GPIO
x
_IPEND
GPIO
x
_IEDGE
GPIO
x
_PPOUTM
GPIO
x
_RDATA
GPIO
x
_DRIVE
GPIO
x
_PUR
GPIO
x
_DR
GPIO
x
_DDR
GPIO
x
_PER
GPIO
x
_IAR
GPIO
x
_IENR
GPIO
x
_IPOLR
GPIO
x
_IPR
GPIO
x
_IESR
GPIO
x
_PPMODE
GPIO
x
_RAWDATA
GPIO
x
_DRIVE
0xF1
n
0
0xF1
n
1
0xF1
n
2
0xF1
n
3
0xF1
n
4
0xF1
n
5
0xF1
n
6
0xF1
n
7
0xF1
n
8
0xF1
n
9
0xF1
n
A
0xF1
n
B
PS
Control Register
Status Register
CTRL
STAT
LVICONTROL
LVISTATUS
PS_CTRL
PS_STAT
LVICONTROL
LVISTATUS
LVICTRL
LVISR
0xF160
0xF161
PWM
Control Register
Fault Control Register
Fault Status/Acknowledge Regis.
Output Control Register
Counter Register
Counter Modulo Register
Value Register 0-5
Deadtime Register 0-1
CTRL
FCTRL
FLTACK
OUT
CNTR
CMOD
VAL0-5
DTIM0-1
PMCTL
PMFCTL
PMFSA
PMOUT
PMCNT
MCM
PMVAL0-5
PMDEADTM0-1
PWM_CTRL
PWM_FCTRL
PWM_FLTACK
PWM_OUT
PWM_CNTR
PWM_CMOD
PWM_VAL0-5
PWM_DTIM0-1
PWM_PMCTL
PWM_PMFCTL
PWM_PMFSA
PWM_PMOUT
PWM_PMCNT
PWM_MCM
PWM_PMVAL0-5
PWM_PMDEADTM
0-1
PWM_PMCTL
PWM_PMFCTL
PWM_PMFSA
PWM_PMOUT
PWM_PMCNT
PWM_PWMCM
PWM_PWMVAL0-5
PWM_PMDEADTM0-
1
PWM_PMDISMAP1-2 0xF04E
0xF040
0xF041
0xF042
0xF043
0xF044
0xF045
0xF046
0xF04C
0xF04B
0xF04D
Disable Mapping Register 1-2
DMAP1-2
PMDISMAP1-2
PWM_DMAP1-2 PWM_PMDISMAP1-
2
0xF04F
Configure Register
Channel Control Register
Port Register
Internal Correction Control Regis.
Source Control Register
CNFG
CCTRL
PORT
ICCTRL
SCTRL
PMCFG
PMCCR
PMPORT
PMICCR
PMSRC
PWM_CNFG
PWM_CCTRL
PWM_PORT
PWM_ICCTRL
PWM_SCTRL
PWM_PMCFG
PWM_PMCCR
PWM_PMPORT
PWM_PMICCR
PWM_PMSRC
PWM_PMCFG
PWM_PMCCR
PWM_PMPORT
PWM_PMICCR
PWM_PMSRC
0xF050
0xF051
0xF052
0xF053
0xF054
SCI
Baud Rate Register
Control Register 1
Control Register 2
Status Register
Data Register
RATE
CTRL1
CTRL2
STAT
DATA
Peripheral Reference Manual
SCIBR
SCICR
SCICR2
SCISR
SCIDR
SCI_RATE
SCI_CTRL1
SCI_CTRL2
SCI_STAT
SCI_DATA
SCI_SCIBR
SCI_SCICR
SCI_SCICR2
SCI_SCISR
SCI_SCIDR
SCI_SCIBR
SCI_SCICR
SCI_SCICR2
SCI_SCISR
SCI_SCIDR
0xF0B0
0xF0B1
0xF0B2
0xF0B3
0xF0B4
Module
Register Name
Data Sheet
Processor
Expert
Acronym
Memory Address
New Acronym
Legacy
Acronym
New Acronym
Legacy Acronym
Start
End