參數(shù)資料
型號: 56F8014
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 61/124頁
文件大?。?/td> 1878K
代理商: 56F8014
Resets
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
61
5.7 Resets
5.7.1
General
5.7.2
Description of Reset Operation
5.7.2.1
The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is
asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET
is released. The general timing is shown in
Figure 5-19
.
Reset Handshake Timing
Figure 5-19 Reset Interface
5.7.3
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,
except the core IRQs with fixed priorities:
ITCN After Reset
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
SW Interrupt 2
SW Interrupt 1
SW Interrupt 0
SW Interrupt LP
These interrupts are enabled at their fixed priority levels.
Table 5-4 Reset Summary
Reset
Priority
Source
Characteristics
Core Reset
RST
Core reset from the SIM
RES
CLK
VAB
PAB
RESET_VECTOR_ADR
READ_ADR
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