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參數(shù)資料
| 型號(hào)： | VT82C586B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI INTEGRATED PERIPHERAL CONTROLLER |
| 中文描述： | 整合的周邊控制器的PCI |
| 文件頁數(shù)： | 58/69頁 |
| 文件大?。?/td> | 393K |
| 代理商： | VT82C586B |
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VT82C586B
Revision 1.0
May 13, 1997
-
52-
Register Descriptions
Offset 33-30 - Primary Activity Detect Status ............. RWC
These bits correspond to the Primary Activity Detect Enable
bits in offset 37-34.
31-8 Reserved
..........................................always read 0
7
Keyboard Controller Access Status.....(KBC_STS)
Set if the keyboard controller is accessed via I/O port
60h.
6
Serial Port Access Status.......................(SER_STS)
Set if the serial port is accessed via I/O ports 3F8-
3FFh, 2F8-2FFh, 3E8-3EFh, or 2E8-2Efh (COM1-4,
respectively).
5
Parallel Port Access Status....................(PAR_STS)
Set if the parallel port is accessed via I/.O ports 278-
27Fh or 378-37Fh (LPT2 or LPT1).
4
Video Access Status.................................(VID_STS)
Set if the video port is accessed via I/O ports 3B0-
3DFh or memory space A0000-BFFFFh.
3
IDE / Floppy Access Status ....................(IDE_STS)
Set if the IDE or floppy devices are accessed via I/O
ports 1F0-1F7h, 170-177h or 3F5h.
2
Reserved
............................................... default=0
1
Primary Interrupt Activity Status......(PIRQ_STS)
Set on the occurrence of a primary interrupt (enabled
via the "Primary Interrupt Channel" register at
Function 3 PCI configuration register offset 44h).
0
ISA Master / DMA Activity Status......(DRQ_STS)
Set on the occurrence of ISA master or DMA activity.
Note:
The bits above correspond to the bits of the Primary
Activity Detect Enable register at offset 34 (see right
hand column of this page): if the corresponding bit is
set in that register, setting of the above bits will cause
the PACT_STS bit to be set (bit-0 of the Global
Status register at offset 28). Setting of PACT_STS
may be set up to enable a "Primary Activity Event":
an SMI will be generated if PACT_EN is set (bit-0 of
the Global Enable register at offset 2Ah) and/or the
GP0 timer will be reloaded if the "GP0 Timer Reload
on Primary Activity" bit is set (bit-0 of the GP Timer
Reload Enable register at offset 38 on this page).
Note:
Bits 3-7 above also correspond to bits 3-7 of the GP
Timer Reload Enable register at offset 38 (see right
hand column of this page): if the corresponding bit is
set in that register, setting the bit in this register will
cause the GP1 timer to be reloaded.
All bits of this register are set by hardware only and may only
be cleared by writing a one to the desired bit. All bits default
to 0.
Offset 37-34 - Primary Activity Detect Enable............... RW
These bits correspond to the Primary Activity Detect Status
bits in offset 33-30.
31-8 Reserved
......................................... always read 0
7
Keyboard Controller Status Enable ..... (KBC_EN)
0
Don't set PACT_STS if KBC_STS is set.....def
1
Set PACT_STS if KBC_STS is set
6
Serial Port Status Enable........................(SER_EN)
0
Don't set PACT_STS if SER_STS is set......def
1
Set PACT_STS if SER_STS is set
5
Parallel Port Status Enable ....................(PAR_EN)
0
Don't set PACT_STS if PAR_STS is set.....def
1
Set PACT_STS if PAR_STS is set
Video Status Enable .................................(VID_EN)
0
Don't set PACT_STS if VID_STS is set......def
1
Set PACT_STS if VID_STS is set
IDE / Floppy Status Enable.....................(IDE_EN)
0
Don't set PACT_STS if IDE_STS is set......def
1
Set PACT_STS if IDE_STS is set
Reserved
....................................................default
Primary INTR Status Enable...............(PIRQ_EN)
0
Don't set PACT_STS if PIRQ_STS is set....def
1
Set PACT_STS if PIRQ_STS is set
4
3
2
1
0
ISA Master / DMA Status Enable.........(DRQ_EN)
0
Don't set PACT_STS if DRQ_STS is set ....def
1
Set PACT_STS if DRQ_STS is set
Note:
Setting of any of the above bits also sets the
PACT_STS bit (bit-0 of offset 28) which causes the
GP0 timer to be reloaded (if PACT_GP0_EN is set)
or generates an SMI (if PACT_EN is set).
Offset 3B-38 - GP Timer Reload Enable ........................ RW
All bits in this register default to 0 on power up.
31-8 Reserved
......................................... always read 0
7
Enable GP1 Timer Reload on KBC Access
1 = setting of KBC_STS causes GP1 timer to reload.
6
Enable GP1 Timer Reload on Serial Port Access
1 = setting of SER_STS causes GP1 timer to reload.
5
Reserved
......................................... always read 0
4
Enable GP1 Timer Reload on Video Access
1 = setting of VID_STS causes GP1 timer to reload.
3
Enable GP1 Timer Reload on IDE/Floppy Access
1 = setting of IDE_STS causes GP1 timer to reload.
2-1
Reserved
......................................... always read 0
0
Enable GP0 Timer Reload on Primary Activity
1 = setting of PACT_STS causes GP0 timer to reload.
Primary activities are enabled via the Primary
Activity Detect Enable register (offset 37-34) with
status recorded in the Primary Activity Detect Status
register (offset 33-30).
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