參數資料
型號： VT82C586B
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI INTEGRATED PERIPHERAL CONTROLLER
中文描述： 整合的周邊控制器的PCI
文件頁數： 11/69頁
文件大?。?/td> 393K
代理商： VT82C586B
9,$7HFKQRORJLHV,QF
VT82C586B
Revision 1.0
May 13, 1997
-5-
Pinouts
Table 1. Pin Descriptions
CPU Interface
Signal Name
CPURST
INTR
Pin No.
142
145
I/O
O
O
Signal Description
CPU Reset.
The VT82C586B asserts CPURST to reset the CPU during power-up.
CPU Interrupt.
INTR is driven by the VT82C586B to signal the CPU that an
interrupt request is pending and needs service.
Non-Maskable Interrupt.
NMI is used to force a non-maskable interrupt to the
CPU. The VT82C586B generates an NMI when either SERR# or IOCHK# is
asserted.
Initialization.
The VT82C586B asserts INIT if it detects a shut-down special cycle
on the PCI bus or if a soft reset is initiated by the register
Stop Clock.
STPCLK# is asserted by the VT82C586B to the CPU in response to
different Power-Management events.
System Management Interrupt.
SMI# is asserted by the VT82C586B to the CPU
in response to different Power-Management events.
Numerical Coprocessor Error.
This signal is tied to the coprocessor error signal on
the CPU.
Ignore Numeric Error.
This pin is connected to the “ignore error” pin on the CPU.
NMI
146
O
INIT
143
O
STPCLK#
148
O
SMI#
149
O
FERR#
141
O
IGNNE#
139
O
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