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參數(shù)資料
| 型號(hào)： | VT82C586B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI INTEGRATED PERIPHERAL CONTROLLER |
| 中文描述： | 整合的周邊控制器的PCI |
| 文件頁數(shù)： | 14/69頁 |
| 文件大?。?/td> | 393K |
| 代理商： | VT82C586B |
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VT82C586B
Revision 1.0
May 13, 1997
-8-
Pinouts
ISA Bus Control (continued)
Signal Name
REFRESH#
Pin No.
29
I/O
B
Signal Description
Refresh.
As an output REFRESH# indicates when a refresh cycle is in progress. As
an input REFRESH# is driven by 16-bit ISA Bus masters to indicate refresh cycle.
Address Enable.
AEN is asserted during DMA cycles to prevent I/O slaves from
misinterpreting DMA cycles as valid I/O cycles.
Interrupt Request.
The IRQ signals provide both system board components and
ISA Bus I/O devices with a mechanism for asynchronously interrupting the CPU.
DMA Request.
The DRQ lines are used to request DMA services from the
VT82C586B’s DMA controller.
Acknowledge.
The DACK# output lines indicate a request for DMA service has
been granted.
Terminal Count.
The VT82C586B asserts TC to DMA slaves as a terminal count
indicator.
ISA Master Request.
(see below pin 137)
Multifunction Pin
Normal Operation:
Speaker Drive.
The SPKR signal is the output of counter 2.
Power-up Strapping:
0/1 = Fixed/flexible IDE I/O base
AEN
15
O
IRQ15, 14, 11-
9, 7-3
DRQ7-5, 3-0
128-129, 127-
126, 61, 71-75
132, 130, 57,
30, 7, 16, 59
133, 131, 58,
31, 33, 18, 60
32
I
I
DACK7:5, 3-0#
O
TC
O
MASTER#
SPKR /
Power-up Strap
(see below)
134
I
B
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