參數(shù)資料
型號(hào)： VT82C586B
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI INTEGRATED PERIPHERAL CONTROLLER
中文描述： 整合的周邊控制器的PCI
文件頁數(shù)： 42/69頁
文件大小： 393K
代理商： VT82C586B
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VT82C586B
Revision 1.0
May 13, 1997
-
36-
Register Descriptions
Offset 4B-48 - Drive Timing Control ............................... RW
The following fields define the Active Pulse Width and
Recovery Time for the IDE DIOR# and DIOW# signals:
31-28 Primary Drive 0 Active Pulse Width
......def=1010b
27-24 Primary Drive 0 Recovery Time
.............def=1000b
23-20 Primary Drive 1 Active Pulse Width
......def=1010b
19-16 Primary Drive 1 Recovery Time
.............def=1000b
15-12 Secondary Drive 0 Active Pulse Width
..def=1010b
11-8 Secondary Drive 0 Recovery Time
.........def=1000b
7-4
Secondary Drive 1 Active Pulse Width
..def=1010b
3-0
Secondary Drive 1 Recovery Time
.........def=1000b
The actual value for each field is the encoded value in the field
plus one and indicates the number of PCI clocks.
Offset 4C - Address Setup Time ...................................... RW
7-6
Primary Drive 0 Address Setup Time
5-4
Primary Drive 1 Address Setup Time
3-2
Secondary Drive 0 Address Setup Time
1-0
Secondary Drive 1 Address Setup Time
For each field above:
00 1T
01 2T
10 3T
11 4T
.....................................................default
Offset 4E - Secondary Non-1F0 Port Access Timing ..... RW
7-4
DIOR#/DIOW# Active Pulse Width
.......def=1111b
3-0
DIOR#/DIOW# Recovery Time
..............def=1111b
The actual value for each field is the encoded value in
the field plus one and indicates the number of PCI
clocks.
Offset 4F - Primary Non-1F0 Port Access Timing` ........ RW
7-4
DIOR#/DIOW# Active Pulse Width
.......def=1111b
3-0
DIOR#/DIOW# Recovery Time
..............def=1111b
The actual value for each field is the encoded value in
the field plus one and indicates the number of PCI
clocks.
Offset 53-50 - UltraDMA33 Extended Timing Control . RW
31
Pri Drive 0 UltraDMA33-Mode Enable Method
0
Enable by using “Set Feature” command.....def
1
Enable by setting bit-6 of this register
30
Pri Drive 0 UltraDMA33-Mode Enable
0
Disable...................................................default
1
Enable UltraDMA33-Mode Operation
29
Pri Drive 0 Transfer Mode
........................read only
0
Based on UltraDMA33 DMA mode......default
1
Based on UltraDMA33 PIO Mode
28-26 Reserved
........................................always reads 0
25-24 Pri Drive 0 Cycle Time
0
2T
1
3T
2
4T
3
5T
....................................................default
23
22
21
Pri Drive 1 UltraDMA33-Mode Enable Method
Pri Drive 1 UltraDMA33-Mode Enable
Pri Drive 1 Transfer Mode
........................read only
20-18 Reserved
........................................always reads 0
17-16 Pri Drive 1 Cycle Time
15
14
13
Sec Drive 0 UltraDMA33-Mode Enable Method
Sec Drive 0 UltraDMA33-Mode Enable
Sec Drive 0 Transfer Mode
........................read only
12-10 Reserved
........................................always reads 0
9-8
Sec Drive 0 Cycle Time
7
6
5
Sec Drive 1 UltraDMA33-Mode Enable Method
Sec Drive 1 UltraDMA33-Mode Enable
Sec Drive 1 Transfer Mode
........................read only
Reserved
........................................always reads 0
Sec Drive 1 Cycle Time
Each byte defines UltraDMA33 operation for the indicated
drive. The bit definitions are the same within each byte.
4-2
1-0
Offset 61-60 - Primary Sector Size .................................. RW
15-12 Reserved
........................................always reads 0
11-0 Number of Bytes Per Sector
................default=200h
Offset 69-68 - Secondary Sector Size .............................. RW
15-12 Reserved
........................................always reads 0
11-0 Number of Bytes Per Sector
................default=200h
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