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參數(shù)資料
| 型號： | VT82C586B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI INTEGRATED PERIPHERAL CONTROLLER |
| 中文描述： | 整合的周邊控制器的PCI |
| 文件頁數(shù)： | 16/69頁 |
| 文件大?。?/td> | 393K |
| 代理商： | VT82C586B |
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VT82C586B
Revision 1.0
May 13, 1997
-10-
Pinouts
UltraDMA-33 Enhanced IDE Interface
Signal Name
Pin No.
I/O
Signal Description
DRDYA# /
DDMARDYA#
/ DSTROBEA
49
I
EIDE Mode:
UltraDMA Mode:
Device DMA Ready A
. Primary channel output flow control
The device may assert DDMARDY# to pause output transfers
Device Strobe A
. Primary channel input data strobe (both edges)
The device may stop DSTROBE to pause input data transfers
EIDE Mode:
I/O Channel Ready B.
Secondary channel device ready
UltraDMA Mode:
Device DMA Ready B
. Secondary channel output flow control
The device may assert DDMARDY# to pause output transfers
Device Strobe B
. Secondary channel input strobe (both edges)
The device may stop DSTROBE to pause input data transfers
EIDE Mode:
Device I/O Read A.
Primary channel device read strobe
UltraDMA Mode:
Host DMA Ready A
. Primary channel input flow control
The host may assert HDMARDY# to pause input transfers
Host Strobe A
. Primary channel output data strobe (both edges)
The host may stop HSTROBE to pause output data transfers
EIDE Mode:
Device I/O Read B.
Secondary channel device read strobe
UltraDMA Mode:
Host DMA Ready B
. Secondary channel input flow control
The host may assert HDMARDY# to pause input transfers
Host Strobe B
. Secondary channel output strobe (both edges)
The host may stop HSTROBE to pause output data transfers
EIDE Mode:
Device I/O Write A.
Primary channel device write strobe
UltraDMA Mode:
Stop A
. Primary channel stop transfer: asserted by the host prior
to initiation of an UltraDMA burst; negated by the host before
data is transferred in an UltraDMA burst. Assertion of STOP by
the host during or after data transfer in UltraDMA mode signals
the termination of the burst.
EIDE Mode:
Device I/O Write B.
Secondary channel device write strobe
UltraDMA Mode:
Stop B
. Secondary channel stop transfer: asserted by the host
prior to initiation of an UltraDMA burst; negated by the host
before data is transferred in an UltraDMA burst. Assertion of
STOP by the host during or after data transfer in UltraDMA mode
signals the termination of the burst.
System Address Transceiver Output Enable.
This signal controls the output
enables of the 245 transceivers that interface the DD[15:0] signals to SA[15:0]. The
transceiver direction controls are driven by MASTER# with DD[15-0] connected to
the “A” side of the transceivers and SA[15-0] connected to the “B” side.
Device DMA Request A.
Primary channel DMA request
Device DMA Request B.
Secondary channel DMA request
Device DMA Acknowledge A.
Primary channel DMA acknowledge
Device DMA Acknowledge B.
Secondary channel DMA acknowledge
I/O Channel Ready A.
Primary channel device ready indicator
DRDYB# /
DDMARDYB#
/ DSTROBEB
89
I
DIORA# /
HDMARDYA#
/ HSTROBEA
50
O
DIORB# /
HDMARDYB#
/ HSTROBEB
54
O
DIOWA# /
STOPA
51
O
DIOWB# /
STOPB
55
O
SOE#
56
O
DDRQA
DDRQB
DDACKA#
DDACKB#
45
46
47
48
I
I
O
O
Note:
Refer to the ISA bus interface pin descriptions for remaining IDE interface pin descriptions (the IDE address, data, and
drive select pins are multiplexed with the ISA bus LA and SA pins). Also, the MASTER# pin description may be found
in the "On Board Plug and Play" pin group (DD / SA transceiver direction control).
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