參數(shù)資料
型號(hào)： VT82C586B
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI INTEGRATED PERIPHERAL CONTROLLER
中文描述： 整合的周邊控制器的PCI
文件頁(yè)數(shù)： 50/69頁(yè)
文件大?。?/td> 393K
代理商： VT82C586B
9,$7HFKQRORJLHV,QF
VT82C586B
Revision 1.0
May 13, 1997
-
44-
Register Descriptions
Power Management Events
Three types of power management events are supported:
1)
ACPI-required Fixed Events
defined in the PM1a_STS
and PM1a_EN registers. These events can trigger either
SCI or SMI
depending on the SCI_EN bit:
PWRBTN# Triggering
RTC Alarm
ACPI Power Management Timer Carry (always SCI)
BIOS Release (always SCI)
2)
ACPI-aware General Purpose Function Events
defined
in the GP_STS and GP_SCI_EN, and GP_SMI_EN
registers. These events can trigger either SCI or SMI
depending on the setting of individual SMI and SCI
enable bits:
EXTSMI triggering (refer to Table 2)
USB Resume
RI# Indicator
3)
Generic Global Events
defined in the GBL_STS and
GBL_EN registers. These registers are mainly used for
SMI:
GP0 and GP1 Timer Time Out
Secondary Event Timer Time Out
Occurrence of Primary Events
(defined in register PACT_STS and PACT_EN)
Legacy USB accesses (keyboard and mouse).
Once enabled, each of the EXTSMI inputs triggers an SCI or
SMI at either the rising or the falling transition of the
corresponding input pin signal. Software can check the status
of the input pins via register EXTSMI_VAL and take proper
actions.
Among many possible actions, the SCI and SMI routine can
change the processor state by programming the P_BLK
registers. The routine can also set the SLP_EN bit to put the
system into one of the two suspend states:
1)
Suspend to Disk (or Soft-Off):
The VDD-5V power
plane is turned off while VDD-5VSB and VDD-RTC
planes remain on.
2)
Power-On-Suspend:
All power planes remain on but the
processor is put in the C3 state.
In either suspend state, there is minimal interface between
powered and non-powered planes.
The VT82C586B allows the following events to wake up the
system from the two suspend states and from the C2 state to
the normal working state (processor in C0 state):
Activation of External Inputs:
PWRBTN#, RI#, GPIO0
and other EXTSMI pins (see table below)
RTC Alarm and ACPI Power Management Timer
(see
table below)
USB Resume Event
(see table below)
Interrupt Events
(always resume independent of any
register setting)
ISA Master or DMA Events
(always resume
independent of any register setting)
The VT82C586B also provides very flexible SCI/SMI steering
and the PWRON control for these events:
Table 6. SCI/SMI/Resume Control for PM Events
Event
Global
SCI/SMI
Control
Individual
Enable Bits
for SCI &
SMI
N
Y
Y
Y
Separate
Control for
PWRON
Resume
Y
Y
N
Y
PWRBTN#
RI#
RTC Alarm
GPIO0
(EXTSMI0)
External SCI/SMI
(non-GPIO0)
ACPI PM Timer
USB Resume
Please refer to the table below on the availability of resume
events in each type of suspend state.
SCI_EN bit
N
N
N
N
Y
N
Always SCI
N
N
N
N
Y
Table 7. Suspend Resume Events and Conditions
Input Trigger
Power Plane Soft Off
Power-On
Suspend
Y
Y
Y
Y
PWRBTN#
RI#
RTC Alarm
GPIO0
(EXTSMI0)
External SCI/SMI
(non-GPIO0)
ACPI PM Timer
USB Resume
PCI/ISA
Interrupts
PCI/ISA
Master/DMA
VDD-5VSB
VDD-5VSB
VBAT
VDD-5VSB
Y
Y
Y
Y
VDD-5V
N
Y
VDD-5V
VDD-5V
VDD-5V
N
N
N
Y
Y
N
VDD-5V
N
N
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