參數(shù)資料
型號(hào)： VT82C586B
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI INTEGRATED PERIPHERAL CONTROLLER
中文描述： 整合的周邊控制器的PCI
文件頁數(shù)： 36/69頁
文件大?。?/td> 393K
代理商： VT82C586B
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VT82C586B
Revision 1.0
May 13, 1997
-
30-
Register Descriptions
Plug and Play Control
Offset 50 - Reserved (Do Not Program) .......................... RW
7-0
Reserved
.......................................... default = 04h
Offset 54 - PCI IRQ Edge / Level Select ......................... RW
7-4
Reserved
........................................ always reads 0
The following bits all default to “l(fā)evel” triggered (0)
3
PIRQA# Invert (edge) / Non-invert (level)
.......(1/0)
2
PIRQB# Invert (edge) / Non-invert (level)
.......(1/0)
1
PIRQC# Invert (edge) / Non-invert (level)
.......(1/0)
0
PIRQD# Invert (edge) / Non-invert (level)
.......(1/0)
Note:
PIRQA-D# normally connect to PCI interrupt pins
INTA-D# (see pin definitions for more information).
Note: The definitions of the fields of the following three
registers were incorrectly documented in some earlier
revisions of this document. The silicon has not changed
and the following definition should be used for all silicon
revisions:
Offset 55 - PNP IRQ Routing 1 ........................................ RW
These bits control routing for external IRQ inputs MIRQ0-1.
7-4
PIRQD# Routing
(see PnP IRQ routing table)
3-0
MIRQ0 Routing
(see PnP IRQ routing table)
Offset 56 - PNP IRQ Routing 2 ........................................ RW
7-4
PIRQA# Routing
(see PnP IRQ routing table)
3-0
PIRQB# Routing
(see PnP IRQ routing table)
Offset 57 - PNP IRQ Routing 3 ........................................ RW
7-4
PIRQC# Routing
(see PnP IRQ routing table)
3-0
MIRQ1 Routing
(see PnP IRQ routing table)
Note: these bits must be set to 0 if Rx48[4]=1 and
Rx59[1]=1 (input IRQ8# on MIRQ1 pin 106)
Offset 58 - PNP IRQ Routing 4 ....................................... RW
These bits control routing for external IRQ input MIRQ2.
7-4
Reserved
........................................always reads 0
3-0
MIRQ2 Routing
(see PnP IRQ routing table)
PnP IRQ Routing Table
0000 Disabled.................................................default
0001 IRQ1
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
1000 Reserved
1001 IRQ9
1010 IRQ10
1011 IRQ11
1100 IRQ12
1101 Reserved
1110 IRQ14
1111 IRQ15
Offset 59 - MIRQ Pin Configuration .............................. RW
7-4
Reserved
........................................always reads 0
3
Power-On Suspend Status Output Enable (Pin 90)
..(3040 Rev F and 3041 Silicon Only))
0
Disable POS Status Output....................default
1
Enable POS Status output on pin 90. Alternate
functions of pin 90 are APICCS# and MIRQ0
if this bit is not set (see bit-0 below).
2
MIRQ2 / MASTER# Selection (Pin 137)
0
MIRQ2...................................................default
1
MASTER#
1
MIRQ1 / KEYLOCK Selection (Pin 106)
0
MIRQ1...................................................default
1
KEYLOCK
0
MIRQ0 / APICCS# Selection (Pin 90)
0
MIRQ0...................................................default
1
APICCS#
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