參數(shù)資料
型號(hào)： VT82C586B
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI INTEGRATED PERIPHERAL CONTROLLER
中文描述： 整合的周邊控制器的PCI
文件頁(yè)數(shù)： 52/69頁(yè)
文件大?。?/td> 393K
代理商： VT82C586B
9,$7HFKQRORJLHV,QF
VT82C586B
Revision 1.0
May 13, 1997
-
46-
Register Descriptions
Power Management I/O-Space Registers
Basic Power Management Control and Status
Offset 1-0 - Power Management Status ....................... RWC
The bits in this register are set only by hardware and can be
reset by software by writing a one to the desired bit position.
15
Wakeup Status
(WAK_STS) ................... default = 0
This bit is set when the system is in the suspend state
and an enabled resume event occurs. Upon setting
this bit, the system automatically transitions from the
suspend state to the normal working state (from C3 to
C0 for the processor).
14-12 Reserved
........................................ always reads 0
11
Power Button Override Status
(PBOR_STS).def=0
This bit is set when the PWRBTN# input pin is
continuously asserted for more than 4 seconds. The
setting of this bit will reset the PB_STS bit and
transition the system into the soft off state.
10
RTC Status
(RTC_STS)........................... default = 0
This bit is set when the RTC generates an alarm (on
assertion of the RTC IRQ signal).
9
8
Reserved
Power Button Status
(PB_STS)............... default = 0
This bit is set when the PWRBTN# signal is asserted
LOW. If the PWRBTN# signal is held LOW for
more than four seconds, this bit is cleared, the
PBOR_STS bit is set, and the system will transition
into the soft off state.
Reserved
........................................ always reads 0
Global Status
(GBL_STS)........................ default = 0
This bit is set by hardware when BIOS_RLS is set
(typically by an SMI routine to release control of the
SCI/SMI lock). When this bit is cleared by software
(by writing a one to this bit position) the BIOS_RLS
bit is also cleared at the same time by hardware.
Bus Master Status
(BM_STS) ................. default = 0
This bit is set when a system bus master requests the
system bus. All PCI master, ISA master and ISA
DMA devices are included.
Reserved
........................................ always reads 0
Timer Carry Status
(TMR_STS)............. default = 0
The bit is set when the 23
rd
(31st) bit of the 24 (32)
bit ACPI power management timer changes.
........................................ always reads 0
7-6
5
4
3-1
0
Offset 3-2 - Power Management Enable ......................... RW
The bits in this register correspond to the bits in the Power
Management Status Register at offset 1-0.
15
Reserved
........................................always reads 0
14-12 Reserved
11
Reserved
........................................always reads 0
........................................always reads 0
10
RTC Enable
(RTC_EN)............................default = 0
This bit may be set to trigger either an SCI or an SMI
(depending on the setting of the SCI_EN bit) to be
generated when the RTC_STS bit is set.
Reserved
........................................always reads 0
Power Button Enable
(PB_EN) ...............default = 0
This bit may be set to trigger either an SCI or an SMI
(depending on the setting of the SCI_EN bit) to be
generated when the PB_STS bit is set.
9
8
7-6
5
Reserved
Global Enable
(GBL_EN).........................default = 0
This bit may be set to trigger either an SCI or an SMI
(depending on the setting of the SCI_EN bit) to be
generated when the GBL_STS bit is set.
........................................always reads 0
4
Reserved
........................................always reads 0
3-1
0
Reserved
ACPI Timer Enable
(TMR_EN)..............default = 0
This bit may be set to trigger either an SCI or an SMI
(depending on the setting of the SCI_EN bit) to be
generated when the TMR_STS bit is set.
........................................always reads 0
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