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參數(shù)資料
| 型號： | VT82C586B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI INTEGRATED PERIPHERAL CONTROLLER |
| 中文描述： | 整合的周邊控制器的PCI |
| 文件頁數(shù)： | 46/69頁 |
| 文件大?。?/td> | 393K |
| 代理商： | VT82C586B |
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VT82C586B
Revision 1.0
May 13, 1997
-
40-
Register Descriptions
Power Management Registers (Function 3)
This section describes the ACPI (Advanced Configuration and
Power Interface) Power Management system of the
VT82C586B. This system supports both ACPI and legacy
power management functions and is compatible with the APM
v1.2 and ACPI v0.9 specifications.
PCI Configuration Space Header
Offset 1-0 - Vendor ID ....................................................... RO
0-7
Vendor ID
................. (1106h = VIA Technologies)
Offset 3-2 - Device ID ......................................................... RO
0-7
Device ID
................(3040h = ACPI Power Mgmt)
Offset 5-4 - Command ....................................................... RW
15-8 Reserved
........................................ always reads 0
7
Address Stepping
........................................fixed at 0
6
Reserved
(parity error response)..................fixed at 0
5
Reserved
(VGA palette snoop) ....................fixed at 0
4
Memory Write and Invalidate
...................fixed at 0
3
Reserved
(special cycle monitoring)............fixed at 0
2
Bus Master
.................................................fixed at 0
1
Memory Space
.............................................fixed at 0
0
I/O Space
.................................................fixed at 0
0
Disable ........ always reads 0 in 3040F and later
1
Enable
Note: In 3040E and earlier silicon, this bit could be
set to 1 to allow access to the Power Management I/O
Register Block (the quadword at offset 20 was used in
that silicon to set the base address for this register
block). Beginning with 3040F silicon, the function of
this bit was moved to offset 41 bit-7 and the base
address register for the PM I/O register block was
moved from to offset 48.
Offset 7-6 - Status ........................................................... RWC
15
Detected Parity Error
........................ always reads 0
14
Signalled System Error
...................... always reads 0
13
Received Master Abort
...................... always reads 0
12
Received Target Abort
...................... always reads 0
11
Signalled Target Abort
...................... always reads 0
10-9 DEVSEL# Timing
00 Fast
01 Medium .....................................default (fixed)
10 Slow
11 Reserved
8
Data Parity Detected
.......................... always reads 0
7
Fast Back to Back
.............................. always reads 1
6-0
Reserved
........................................ always reads 0
Offset 8 - Revision ID (nnh) .............................................. RO
7-4
Silicon Version Code
0
OEM Version ("3040 Silicon")
1
Production Version ("3041 Silicon")
2-F -reserved for future use-
3-0
Silicon Revision Code
OEM Version
0
Revision E ("3040E")
1
Revision F ("3040F")
2-F -reserved for future use-
Production Version
0
Revision A ("3041" or "3041A")
1-F -reserved for future use-
Programming and pin differences between the above silicon
versions and revisions are indicated in this document in the
appropriate section. Marking specifications corresponding to
the above versions and revisions are also included in the
Mechanical Specifications section of this document.
Offset 9 - Programming Interface (00h) .......................... RO
The value returned by this register may be changed by writing
the desired value to PCI Configuration Function 3 offset 61h.
Offset A - Sub Class Code (00h) ....................................... RO
The value returned by this register may be changed by writing
the desired value to PCI Configuration Function 3 offset 62h.
Offset B - Base Class Code (00h) ...................................... RO
The value returned by this register may be changed by writing
the desired value to PCI Configuration Function 3 offset 63h.
Offset 0D - Latency Timer ............................................... RW
7-0
Timer Value
..........................................default = 16h
Offset 0E - Header Type (00h) ......................................... RO
Offset 23-20 - I/O Register Base Address (3040E only) RW
31-16 Reserved
........................................always reads 0
15-8 Power Management I/O Register Base Address.
Port Address for the base of the 256-byte Power
Management I/O Register block, corresponding to
AD[15:8]. The "I/O Space" bit at offset 5-4 bit-0
enables access to this register block.
7-0
00000001b
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