參數(shù)資料
型號: TLV320AIC34_1
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: FOUR-CHANNEL, LOW-POWER AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
中文描述: 四通道,低功耗音頻編解碼器的便攜式音頻/電話
文件頁數(shù): 90/94頁
文件大小: 905K
代理商: TLV320AIC34_1
www.ti.com
TLV320AIC34
SLAS538A–OCTOBER 2007–REVISED NOVEMBER 2007
Page 0 / Register 108:
Passive Analog Signal Bypass Selection During Power Down Register
(1)
READ/
WRITE
R/W
RESET
VALUE
0
BIT
DESCRIPTION
D7
LINE2RM_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOM_x.
LINE2RP_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOP_x.
LINE1RM_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOM_x.
LINE1RP_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOP_x.
LINE2LM_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOM_x.
LINE2LP_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOP_x.
LINE1LM_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOM_x.
LINE1LP_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOP_x.
D6
R/W
0
D5
R/W
0
D4
R/W
0
D3
R/W
0
D2
R/W
0
D1
R/W
0
D0
R/W
0
(1)
Based on the settings of this register, if BOTH LINE1 and LINE2 inputs are routed to the output at the same time, then the two switches
used for the connection short the two input signals together on the output terminals. The shorting resistance between the two input
terminals is two times the bypass switch resistance (Rdson). In general, this condition of shorting should be avoided, as higher drive
currents are likely to occur on the circuitry that feeds these two input terminals of this device.
Page 0 / Register 109:
DAC Dynamic Range Selection Register
READ/
WRITE
R/W
RESET
VALUE
00
BIT
DESCRIPTION
D7–D6
DAC Dynamic Range Adjustment
00: Default (Dynamic range specified in electrical characteristics table)
01: Dynamic range enhancement level 1
10: Reserved
11: Dynamic range enhancement level 2
Reserved. Write only zeros to these register bits.
D5–D0
R/W
00 0000
Page 0 / Register 110–127:
Reserved Registers
READ/
WRITE
R
RESET
VALUE
0000 0000
BIT
DESCRIPTION
D7–D0
Reserved. Do not write to these registers.
Page 1 / Register 0:
Page Select Register
BIT
READ/
WRITE
X
R/W
RESET
VALUE
0000 000
0
DESCRIPTION
D7–D1
D0
Reserved. Write only zeros to these register bits.
Page Select Bit
Writing zero to this bit sets page 0 as the active page for subsequent register accesses. Writing a one to
this bit sets page 1 as the active page for subsequent register accesses. It is recommended that the user
read this register bit back after each write, to ensure that the proper page is being accessed for future
register read/writes. This register has the same functionality on page 0 and page 1.
90
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TLV320AIC34
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