參數(shù)資料
型號(hào)： TLV320AIC34_1
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： FOUR-CHANNEL, LOW-POWER AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
中文描述： 四通道，低功耗音頻編解碼器的便攜式音頻/電話
文件頁數(shù)： 56/94頁
文件大小： 905K
代理商： TLV320AIC34_1
www.ti.com
TLV320AIC34
SLAS538A–OCTOBER 2007–REVISED NOVEMBER 2007
Page 0 / Register 10:
Audio Serial Data Interface Control Register C
READ/
WRITE
R/W
RESET
VALUE
0000 0000
BIT
DESCRIPTION
D7–D0
Audio Serial Data Word Offset Control
This register determines where valid data is placed or expected in each frame, by controlling the offset
from the beginning of the frame where valid data begins. The offset is measured from the rising edge of
the word clock when in DSP mode.
0000 0000: Data offset = 0 bit clocks
0000 0001: Data offset = 1 bit clock
0000 0010: Data offset = 2 bit clocks
…
Note: In continuous transfer mode, the maximum offset is 17 for I
2
S/LJF/RJF modes and 16 for DSP
mode. In 256-clock mode, the maximum offset is 242 for I
2
S/LJF/RJF and 241 for DSP modes.
1111 1110: Data offset = 254 bit clocks
1111 1111: Data offset = 255 bit clocks
Page 0 / Register 11:
Audio Codec Overflow Flag Register
READ/
WRITE
R
RESET
VALUE
0
BIT
DESCRIPTION
D7
Left-ADC Overflow Flag
This is a sticky bit, so it stays set if an overflow occurs, even if the overflow condition is removed. The
register bit is reset to 0 after it is read.
0: No overflow has occurred.
1: An overflow has occurred.
Right-ADC Overflow Flag
This is a sticky bit, so it stays set if an overflow occurs, even if the overflow condition is removed. The
register bit is reset to 0 after it is read.
0: No overflow has occurred.
1: An overflow has occurred.
Left-DAC Overflow Flag
This is a sticky bit, so it stays set if an overflow occurs, even if the overflow condition is removed. The
register bit is reset to 0 after it is read.
0: No overflow has occurred.
1: An overflow has occurred.
Right DAC Overflow Flag
This is a sticky bit, so it stays set if an overflow occurs, even if the overflow condition is removed. The
register bit is reset to 0 after it is read.
0: No overflow has occurred.
1: An overflow has occurred.
PLL R Value
0000: R = 16
0001 : R = 1
0010 : R = 2
0011 : R = 3
0100 : R = 4
…
1110: R = 14
1111: R = 15
D6
R
0
D5
R
0
D4
R
0
D3–D0
R/W
0001
56
Submit Documentation Feedback
Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s):
TLV320AIC34
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