參數(shù)資料
型號: TLV320AIC34_1
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: FOUR-CHANNEL, LOW-POWER AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
中文描述: 四通道,低功耗音頻編解碼器的便攜式音頻/電話
文件頁數(shù): 81/94頁
文件大?。?/td> 905K
代理商: TLV320AIC34_1
www.ti.com
TLV320AIC34
SLAS538A–OCTOBER 2007–REVISED NOVEMBER 2007
Page 0 / Register 86:
LEFT_LOP_x and LEFT_LOM_x Output Level Control Register
READ/
WRITE
R/W
RESET
VALUE
0000
BIT
DESCRIPTION
D7–D4
LEFT_LOP_x and LEFT_LOM_x Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
LEFT_LOP_x and LEFT_LOM_x Mute
0: LEFT_LOP_x and LEFT_LOM_x is muted.
1: LEFT_LOP_x and LEFT_LOM_x is not muted.
Reserved. Do not write to this register bit.
LEFT_LOP_x and LEFT_LOM_x Volume Control Status
0: All programmed gains to LEFT_LOP_x and LEFT_LOM_x have been applied.
1: Not all programmed gains to LEFT_LOP_x and LEFT_LOM_x have been applied yet.
LEFT_LOP_x and LEFT_LOM_x Power Status
0: LEFT_LOP_x and LEFT_LOM_x is not fully powered up.
1: LEFT_LOP_x and LEFT_LOM_x is fully powered up.
D3
R/W
0
D2
D1
R
R
0
1
D0
R
0
Page 0 / Register 87:
LINE2LP_x and LINE2LM_x to RIGHT_LOP_x and RIGHT_LOM_x Volume Control
Register
READ/
WRITE
R/W
RESET
VALUE
0
BIT
DESCRIPTION
D7
LINE2LP_x and LINE2LM_x Output Routing Control
0: LINE2LP_x and LINE2LM_x is not routed to RIGHT_LOP_x and RIGHT_LOM_x.
1: LINE2LP_x and LINE2LM_x is routed to RIGHT_LOP_x and RIGHT_LOM_x.
LINE2LP_x and LINE2LM_x to RIGHT_LOP_x and RIGHT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see
Table 7
.
D6–D0
R/W
000 0000
Page 0 / Register 88:
PGA_LP_x and PGA_LM_x to RIGHT_LOP_x and RIGHT_LOM_x Volume Control
Register
READ/
WRITE
R/W
RESET
VALUE
0
BIT
DESCRIPTION
D7
PGA_LP_x and PGA_LM_x Output Routing Control
0: PGA_LP_x and PGA_LM_x is not routed to RIGHT_LOP_x and RIGHT_LOM_x.
1: PGA_LP_x and PGA_LM_x is routed to RIGHT_LOP_x and RIGHT_LOM_x.
PGA_LP_x and PGA_LM_x to RIGHT_LOP_x and RIGHT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see
Table 7
.
D6–D0
R/W
000 0000
Page 0 / Register 89:
DAC_L1 to RIGHT_LOP_x and RIGHT_LOM_x Volume Control Register
READ/
WRITE
R/W
RESET
VALUE
0
BIT
DESCRIPTION
D7
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to RIGHT_LOP_x and RIGHT_LOM_x.
1: DAC_L1 is routed to RIGHT_LOP_x and RIGHT_LOM_x.
DAC_L1 to RIGHT_LOP_x and RIGHT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see
Table 7
.
D6–D0
R/W
000 0000
Copyright 2007, Texas Instruments Incorporated
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TLV320AIC34
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