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I
2
C BUS DEBUG IN A GLITCHED SYSTEM
Occasionally, some systems may encounter noise or glitches on the I
2
C bus. In the unlikely event that this
affects bus performance, then it can be useful to use the I
2
C debug register. This feature terminates the I
2
C bus
error, allowing this I
2
C device and system to resume communications. The I
2
C bus error detector is enabled by
default. The TLV320AIC34 I
2
C error detector status can be read from page 0, register 107, bit D0. If desired, the
detector can be disabled by writing to page 0, register 107, bit D2.
DIGITAL AUDIO DATA SERIAL INTERFACE
Audio data is transferred between host processor(s) and the TLV320AIC34 via the two digital audio data serial
interfaces. The two data serial interfaces on this device are identical and very flexible, supporting left- or
right-justified data options, support for I
2
S or PCM protocols, programmable data length options, a TDM mode for
multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to
communicate directly with multiple devices within a system.
Audio Serial Data Bus
DOUT_x
DIN_x
BCLK_x
WCLK_x
GPIO2_x
GPIO1_x
B0233-01
TLV320AIC34
SLAS538A–OCTOBER 2007–REVISED NOVEMBER 2007
Similarly, in the case of an I
2
C register read, after the device has sent out the 8-bit data from the addressed
register, if the master issues an ACKNOWLEDGE, the slave takes over control of the SDA bus and transmits for
the next 8 clocks the data of the next incremental register. Note that incremental read/write operation does not
continue past a page boundary. The user should not attempt to read/write past the end of a page, because this
may result in undesirable operation.
A key characteristic of the TLV320AIC34 is its ability for separate data converters to operate at different sampling
rates simultaneously. This requires use of the two data busses at different rates at the same time, which is fully
supported by this device. In addition, the two data busses can operate at the same time with different data
transfer format configurations. This is useful, for example, in a cellular handset application, where the A-channel
data bus can communicate with a Bluetooth transceiver device using PCM format at an 8-ksps sampling rate,
transferring mono or stereo data with A-channel mono or stereo ADCs and DACs. At the same time, the B
channel data bus can be communicating with a multimedia applications processor in I
2
S format at a 44.1-ksps
sampling rate, transferring mono or stereo data with B-channel mono or stereo ADCs or DACs.
Each data serial interface also can use two sets of terminals for clock communication between external devices,
with the particular terminals used being controlled through register programming. This configuration is shown in
Figure 19
for the A interface, with the B interface having identical flexibility. The TLV320AIC34 provides
independent control over both the formats and clock mux configurations of the two interfaces, so the two busses
can be configured differently from each other.
Figure 19. Internal Multiplex Capability on Each I
2
S Bus, Enabling Communication
With Multiple External Devices
Copyright 2007, Texas Instruments Incorporated
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