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ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
In addition to the input bypass path described previously, the TLV320AIC34 also includes the ability to route the
ADC PGA output signals past the ADC, for mixing with other analog signals and then direct connection to the
output drivers of the same partition. These bypass functions are described in more detail in the sections on
output mixing and output driver configurations.
INPUT IMPEDANCE AND VCM CONTROL
The TLV320AIC34 includes several programmable settings to control analog input terminals, particularly when
they are not selected for connection to an ADC PGA. The default option allows unselected inputs to be put into a
high-impedance state, such that the input impedance seen looking into the device is extremely high. Note,
however, that the terminals on the device do include protection diode circuits connected to AVDD_ADC and
AVSS_ADC. Thus, if any voltage is driven onto a terminal approximately one diode drop (~0.6 V) above
AVDD_ADC or one diode drop below AVSS_ADC, these protection diodes begin conducting current, resulting in
an effective impedance that no longer appears as a high-impedance state.
PASSIVE ANALOG BYPASS DURING POWER DOWN
Programming the TLV320AIC34 to passive analog bypass occurs by configuring the output stage switches for
pass-through. This is done by opening switches SW-L0, SW-L3, SW-R0, SW-R3 and closing either SW-L1 or
SW-L2 and SW-R1 or SW-R2. See
Figure 32
,
Passive Analog Bypass Mode Configuration
. Programming this
mode is done by writing to page 0, register 108.
TLV320AIC34
SLAS538A–OCTOBER 2007–REVISED NOVEMBER 2007
Another programmable option for unselected analog inputs is to hold them weakly at the common-mode input
voltage of the ADC PGA (which is determined by an internal band-gap voltage reference). This is useful to keep
the ac-coupling capacitors connected to analog inputs biased up at a normal dc level, thus avoiding the need for
them to charge up suddenly when the input is changed from being unselected to selected for connection to an
ADC PGA. This option is controlled in page 0, registers 20 and 23 of each partition. The user should ensure this
option is disabled when an input is selected for connection to an ADC PGA or selected for the analog input
bypass path, because it can corrupt the recorded input signal if left operational when an input is selected.
In most cases, the analog input terminals on the TLV320AIC34 should be ac-coupled to analog input sources,
the only exception to this generally being if an ADC is being used for dc voltage measurement. The ac-coupling
capacitor causes a high-pass filter pole to be inserted into the analog signal path, so the size of the capacitor
must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed
analog signal. The input impedance of the analog inputs when selected for connection to an ADC PGA varies
with the setting of the input level control, starting at approximately 20 k
with an input level control setting of
0 dB, and increasing to approximately 80 k
when the input level control is set at –12 dB. For example, using a
0.1-
μ
F ac-coupling capacitor at an analog input results in a high-pass filter pole of 80 Hz when the 0-dB input
level control setting is selected.
Connecting the LINE1LP_x input signal to the LEFT_LOP_x terminal is done by closing SW-L1 and opening
SW-L0; this action is done by writing a 1 to page 0, register 108, bit D0. Connecting the LINE2LP_x input signal
to the LEFT_LOP_x terminal is done by closing SW-L2 and opening SW-L0; this action is done by writing a 1 to
page 0, register 108, bit D2. Connecting the LINE1LM_x input signal to the LEFT_LOM_x terminal is done by
closing SW-L4 and opening SW-L3; this action is done by writing a 1 to page 0, register 108, bit D1. Connecting
the LINE2LM_x input signal to the LEFT_LOM_x terminal is done by closing SW-L5 and opening SW-L3; this
action is done by writing a 1 to page 0, register 108, bit D3.
Connecting the LINE1RP_x input signal to the RIGHT_LOP_x terminal is done by closing SW-R1 and opening
SW-R0; this action is done by writing a 1 to page 0, register 108, bit D4. Connecting the LINE2RP_x input signal
to the RIGHT_LOP_x terminal is done by closing SW-R2 and opening SW-R0; this action is done by writing a 1
to page 0, register 108, bit D6. Connecting the LINE1RM_x input signal to the RIGHT_LOM_x terminal is done
by closing SW-R4 and opening SW-R3; this action is done by writing a 1 to page 0, register 108, bit D5.
Connecting the LINE2RM_x input signal to the RIGHT_LOM_x terminal is done by closing SW-R5 and opening
SW-R3; this action is done by writing a 1 to page 0, register 108, bit D7. A diagram of the passive analog bypass
mode configuration can be seen in
Figure 32
.
In general, connecting two switches to the same output terminal should be avoided, as this error shorts two input
signals together, and would likely cause distortion of the signal as the two signals are in contention; poor
frequency response would also likely occur.
Copyright 2007, Texas Instruments Incorporated
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