![](http://datasheet.mmic.net.cn/370000/STDL130_datasheet_16733657/STDL130_592.png)
Samsung ASIC
4-175
STDL130
PvOTyz_ABB_LP
Analog Tri-state Output Buffers with Separate Bulk-Bias
Switching Characteristics
(Typical process, 25
°
C, 1.8V, t
R
/t
F
= 0.20ns, CL: Capacitive Load[pF])
POT1_ABB_LP
POT2_ABB_LP
Path
Parameter
Delay [ns]
CL = 50.0pF
20.215
22.775
9.897
12.442
20.215
22.775
9.948
12.512
0.670
0.531
20.215
22.775
10.013
12.578
0.704
0.565
<
Delay Equations [ns]
Group1*
1.333 + 0.378*CL
1.555 + 0.424*CL
0.983 + 0.178*CL
1.575 + 0.217*CL
1.333 + 0.378*CL
1.555 + 0.424*CL
1.030 + 0.178*CL
1.645 + 0.217*CL
0.670 + 0.000*CL
0.531 + 0.000*CL
1.333 + 0.378*CL
1.555 + 0.424*CL
1.096 + 0.178*CL
1.710 + 0.217*CL
0.704 + 0.000*CL
0.565 + 0.000*CL
Group2*
1.329 + 0.378*CL
1.547 + 0.425*CL
0.984 + 0.178*CL
1.574 + 0.217*CL
1.329 + 0.378*CL
1.547 + 0.425*CL
1.032 + 0.178*CL
1.644 + 0.217*CL
0.670 + 0.000*CL
0.531 + 0.000*CL
1.329 + 0.378*CL
1.547 + 0.425*CL
1.097 + 0.178*CL
1.712 + 0.217*CL
0.704 + 0.000*CL
0.564 + 0.000*CL
Group3*
1.326 + 0.378*CL
1.541 + 0.425*CL
0.983 + 0.178*CL
1.577 + 0.217*CL
1.329 + 0.378*CL
1.541 + 0.425*CL
1.035 + 0.178*CL
1.647 + 0.217*CL
0.670 + 0.000*CL
0.531 + 0.000*CL
1.329 + 0.378*CL
1.541 + 0.425*CL
1.097 + 0.178*CL
1.709 + 0.217*CL
0.704 + 0.000*CL
0.565 + 0.000*CL
A to PAD
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
tPLZ
tPHZ
tR
tF
tPLH
tPHL
tPLZ
tPHZ
TN to PAD
EN to PAD
*Group1 : CL < 50, *Group2 : 50 =
Path
Parameter
Delay [ns]
CL = 50.0pF
13.606
12.068
6.968
6.837
13.606
12.068
7.019
6.906
0.511
0.824
13.606
12.068
7.084
6.971
0.545
0.858
<
Delay Equations [ns]
Group1*
0.929 + 0.254*CL
0.834 + 0.225*CL
0.900 + 0.121*CL
0.985 + 0.117*CL
0.929 + 0.254*CL
0.834 + 0.225*CL
0.948 + 0.121*CL
1.053 + 0.117*CL
0.511 + 0.000*CL
0.824 + 0.000*CL
0.929 + 0.254*CL
0.834 + 0.225*CL
1.014 + 0.121*CL
1.119 + 0.117*CL
0.545 + 0.000*CL
0.858 + 0.000*CL
Group2*
0.928 + 0.254*CL
0.830 + 0.225*CL
0.901 + 0.121*CL
0.985 + 0.117*CL
0.928 + 0.254*CL
0.830 + 0.225*CL
0.951 + 0.121*CL
1.054 + 0.117*CL
0.511 + 0.000*CL
0.824 + 0.000*CL
0.928 + 0.254*CL
0.830 + 0.225*CL
1.017 + 0.121*CL
1.120 + 0.117*CL
0.545 + 0.000*CL
0.858 + 0.000*CL
Group3*
0.925 + 0.254*CL
0.821 + 0.225*CL
0.900 + 0.121*CL
0.984 + 0.117*CL
0.925 + 0.254*CL
0.821 + 0.225*CL
0.951 + 0.121*CL
1.054 + 0.117*CL
0.511 + 0.000*CL
0.824 + 0.000*CL
0.925 + 0.254*CL
0.821 + 0.225*CL
1.016 + 0.121*CL
1.120 + 0.117*CL
0.545 + 0.000*CL
0.858 + 0.000*CL
A to PAD
tR
tF
tPLH
tPHL
tR
tF
tPLH
tPHL
tPLZ
tPHZ
tR
tF
tPLH
tPHL
tPLZ
tPHZ
TN to PAD
EN to PAD
*Group1 : CL < 50, *Group2 : 50 =