參數(shù)資料
型號: ST7285C
廠商: 意法半導體
英文描述: 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
中文描述: 8位微控制器48,000鐵路發(fā)展策略光盤,3K內存,ADC,兩個定時器,2個SPI,I2C和脊髓損傷接口
文件頁數(shù): 95/117頁
文件大小: 748K
代理商: ST7285C
95/117
ST7285C
CONTROL TIMING
(Cont’d)
1. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge
the undefined region of the falling edge of SCL
2. The maximum hold time of the START condition only has to be met if the interface does not stretch the
low period of SCL signal
Cb = total capacitance of one bus line in pF
Figure 44. Definition of Timing Terminology
I
2
C BUS INTERFACE
Parameter
Standard I
2
C
Min
Fast I
2
C
Min
Symbol
Unit
Max
Max
Bus free time between a STOP and START
condition
Hold time START condition. After this period,
the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
4.7
1.3
Tubs
m
s
4.0
0.6
Thd:sta
μ
s
4.7
4.0
4.7
0 (1)
250
1.3
0.6
0.6
0 (1)
100
Tlow
Thigh
Tsu:sta
Thd:dat
Tsu:dat
Tr
Tf
Tsu:sto
Cb
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
ns
pF
0.9(2)
1000
300
20+0.1Cb
20+0.1Cb
0.6
300
300
4.0
400
400
Tbuf
Tlow Tr
Tf
Thd:sta
Tsp
Thd:sta
Thigh
Thd:dat
Tsu:dat Tsu:sta
Tsu:sto
SDA
SCL
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