- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄385871 > ST7285C (意法半導(dǎo)體) 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES PDF資料下載
參數(shù)資料
| 型號(hào)： | ST7285C |
| 廠(chǎng)商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000鐵路發(fā)展策略光盤(pán)，3K內(nèi)存，ADC，兩個(gè)定時(shí)器，2個(gè)SPI，I2C和脊髓損傷接口 |
| 文件頁(yè)數(shù)： | 64/117頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | ST7285C |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)當(dāng)前第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)
64/117
ST7285C
4.6 A/D CONVERTER (ADC)
4.6.1 Introduction
The on-chip Analog to Digital Converter peripheral
is a single 8-bit successive approximation ratio-
metric monotonic ADC, to which up to 8 different
analog voltages (depending on device specifica-
tion as illustrated in Block Diagram) may be ap-
plied from external sources. The result of the con-
version is stored in the 8-bit Data Register. The A/
D converter is controlled through the ADC Control/
Status Register.
4.6.2 Functional Description
The A/D converter is enabled by setting the A/D
Converter ON bit (ADON) in the ADC Control/Sta-
tus Register. A delay time is then required for the
converter to stabilize (typically 10
μ
s, see Electrical
Characteristics)).
When the A/D function is enabled, the associated
pins (see MCU Block Diagram) may be used as
analog inputs. The inputs must first be enabled for
analog input by setting the corresponding bit(s) of
the relevant Port Configuration Register as de-
scribed in the Section on I/O Ports. Bits CH2 to
CH0 of the A/D Converter Control/Status Register
may then be coded to select the channel to be
converted. Using a pin, or pins, as analog inputs
does not affect the ability to read the port as logic
inputs.
The A/D converter may be disabled by resetting
the ADON bit. This feature allows the reduction of
power consumption when no conversion is in
progress. The A/D converter is disabled after Pow-
er-On and external resets.
When enabled, the A/D converter performs a con-
tinuous conversion of the selected channel. When
a conversion is completed (16
μ
s for f
CPU
= 4
MHz), the result is loaded into the read only Result
Data Register and the COCO (Conversion Com-
plete) flag is set. No interrupt is generated. Any
write to the A/D Converter Control/Status Register
aborts the current conversion, resets the COCO
flag and starts a new conversion.
The A/D converter is ratiometric. An input voltage
equal to, or greater than V
DD ,
converts to FFh (full
scale) without overflow indication if greater. An in-
put voltage equal to, or lower than V
SS
converts to
00h. The conversion is monotonic: the results nev-
er decrease if the analog input does not and never
increase if the analog input does not.
The 8-bit conversion is accurate to within 2 LSB.
The minimal conversion time is 32 ADC clock cy-
cles (16
μ
s
if A/D clock frequency at 2 MHz). The
A/D converter clock is generated from the CPU
clock divided by 2.
The high and low level reference voltages are con-
nected to V
DD
and V
SS
. Conversion accuracy may
therefore be degraded by voltage drops and noise
in the event of heavily loaded or badly decoupled
power supply lines.
The A/D converter is not affected by WAIT mode
but, in power sensitive applications, it can be disa-
bled before entering this mode. When the MCU
enters HALT mode with the A/D converter ena-
bled, the A/D clocks are stopped and the converter
is disabled until the HALT mode is exited and the
start-up delay has elapsed. A stabilisation time is
also required before accurate conversions can be
performed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST72T85A5Q6 | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| ST730C08L3 | PHASE CONTROL THYRISTORS |
| ST730C08L3L | PHASE CONTROL THYRISTORS |
| ST730C12L0 | PHASE CONTROL THYRISTORS |
| ST730C12L0L | PHASE CONTROL THYRISTORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST7-28B56 | 功能描述:電源變壓器 SPLIT BOBBIN HORZ MOUNT XFMR RoHS:否 制造商:Triad Magnetics 功率額定值:12 VA 初級(jí)電壓額定值:115 V / 230 V 次級(jí)電壓額定值:12 V / 24 V 安裝風(fēng)格:SMD/SMT 一次繞組:Dual Primary Winding 二次繞組:Dual Secondary Winding 長(zhǎng)度:2.5 in 寬度:2 in 高度:1.062 in |
| ST72A | 制造商:DGS 功能描述: |
| ST72C104G1B6 | 功能描述:8位微控制器 -MCU Flash 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72C104G1M1 | 制造商:STMicroelectronics 功能描述:8-BIT MICROCONTROLLER - Bulk |
| ST72C104G1M6 | 功能描述:8位微控制器 -MCU Flash 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。