參數(shù)資料
型號(hào)： ST7285C
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
中文描述： 8位微控制器48,000鐵路發(fā)展策略光盤，3K內(nèi)存，ADC，兩個(gè)定時(shí)器，2個(gè)SPI，I2C和脊髓損傷接口
文件頁數(shù)： 47/117頁
文件大?。?/td> 748K
代理商： ST7285C
47/117
ST7285C
SERIAL PERIPHERAL INTERFACE
(Cont’d)
4.4.4 Signal Description
The four basic signals (MOSI, MISO, SCK andSS)
are described in the following paragraphs. Each
signal function is described for both the Master
and Slave mode.
The SPE (Serial Peripheral Enable) bit of the SPI
Control Register enables and disables the SPI (ac-
tive high); when the SPI is enabled the associated
alternate functions will be attributed to the relevant
I/O pins.
The SPI baud rate is the CPU clock divided by a
factor defined by software (2, 4, 16, 32).
4.4.5 Master Out Slave In (MOSI)
The MOSI pin is configured as a data output in the
Master (mode) device and as a data input in the
Slave (mode) device.
In this manner data is transferred serially from a
Master to a Slave on this line, most significant bit
first, least significant bit last. The timing diagrams
shown in the ELECTRICAL CHARACTERISTICS
section, CONTROL TIMING subsection, illustrate
SPI timing and show the relationship between data
and clock (SCK).
Four possible timing relationships may be chosen
by using control bits CPOL and CPHA. The Master
device always allows data to be applied on the
MOSI line a half-cycle before the clock edge
(SCK) to allow the Slave device to latch the data.
Both the Slave device(s) and a Master device
must be programmed to similar modes for proper
data transfer.
When the Master device transmits data to a sec-
ond (Slave) device via the MOSI line, the Slave
device responds by sending data to the Master de-
vice via the MISO line. This implies full duplex
transmission with both data out and data in syn-
chronized with the same clock signal (which is pro-
vided by the Master device). Thus, the byte trans-
mitted is replaced by the byte received and elimi-
nates the need for separate transmit-empty and
receiver-full status bits. A single status bit SPIF) is
used to signify that the I/O operation is complete.
Configuration of the MOSI pin is a function of the
MSTR bit in the Serial Peripheral Control Register
(SPCR). When operating as a Master, the user
should set the MSTR bit, defining the MOSI pin as
an output
4.4.6 Master In Slave Out (MISO)
The MISO pin is configured as an input in a Master
(mode) device and as an output in a Slave (mode)
device. In this manner data is transferred serially
from a Slave to a Master on this line, most signifi-
cant bit first,least significant bit last. The MISO pin
of a Slave device is placed in the high-impedance
state if it is not selected by the Master, i.e. itsSS
pin is at a logic high level. The timing diagram
shows the relationship between data and clock
(SCK). Four possible timing relationships may be
chosen by using control bits CPOL and CPHA. The
Master device always allows data to be applied on
the MOSI line a half-cycle before the clock edge
(SCK) in order for the Slave device to latch the da-
ta.
Note.
The Slave device and a Master device must
be programmed with similar timing modes for
proper data transfer.
When the Master device transmits data to a Slave
device via the MOSI line, the Slave device re-
sponds by sending data to Master device via the
MISO line. This implies full duplex transmission
with both data out and data in synchronized with
the same clock signal (one which is provided by
the Master device.) Thus, the byte transmitted is
replaced by the byte received and eliminates the
need for separate transmit-empty and receiver-full
bits. A single status bit (SPIF) in the Serial Periph-
eral Status Register (SPSR) is used to signify that
the I/O operation is complete.
In the Master device, the MSTR control bit in the
Serial Peripheral Control Register (SPCR) should
be set (by the program) to allow the Master device
to receive data on its MISO pin. In the Slave de-
vice, its MISO pin is enabled by the logic high level
present on theSS pin: i.e. ifSS = 1 the MISO pin is
placed in the high-impedance state, whereas ifSS
= 0 the MISO pin is an output for the Slave device.
相關(guān)PDF資料
PDF描述
ST72T85A5Q6 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
ST730C08L3 PHASE CONTROL THYRISTORS
ST730C08L3L PHASE CONTROL THYRISTORS
ST730C12L0 PHASE CONTROL THYRISTORS
ST730C12L0L PHASE CONTROL THYRISTORS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST7-28B56 功能描述:電源變壓器 SPLIT BOBBIN HORZ MOUNT XFMR RoHS:否 制造商:Triad Magnetics 功率額定值:12 VA 初級(jí)電壓額定值:115 V / 230 V 次級(jí)電壓額定值:12 V / 24 V 安裝風(fēng)格:SMD/SMT 一次繞組:Dual Primary Winding 二次繞組:Dual Secondary Winding 長(zhǎng)度:2.5 in 寬度:2 in 高度:1.062 in
ST72A 制造商:DGS 功能描述:
ST72C104G1B6 功能描述:8位微控制器 -MCU Flash 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST72C104G1M1 制造商:STMicroelectronics 功能描述:8-BIT MICROCONTROLLER - Bulk
ST72C104G1M6 功能描述:8位微控制器 -MCU Flash 4K SPI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*