參數(shù)資料
型號: ST7285C
廠商: 意法半導體
英文描述: 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
中文描述: 8位微控制器48,000鐵路發(fā)展策略光盤,3K內(nèi)存,ADC,兩個定時器,2個SPI,I2C和脊髓損傷接口
文件頁數(shù): 68/117頁
文件大小: 748K
代理商: ST7285C
68/117
ST7285C
4.8 RDS DEMODULATOR
The RDS demodulator is a fully digital Radio Data
System demodulator. The module includes 57KHz
carrier recovery, RDS clock (1187.5Hz) recovery,
bi-phase decoder, fast ARI indicator and signal
quality indicator. the module is controlled through
ST7 registers. The RDS signal is fed inthrough the
pin RDSCOMP. The reference frequency is de-
rived from the ST7 quartz oscillator. Therefore, the
quartz frequency must be 8.664MHz.
4.8.1 Features
– Pure digital RDS demodulator without external
components.
– Phase polarity data extractor.
– Phase integral data extractor.
– Data extractor selectable:
a) automatically via quality detector;
b) via software.
– Selectable quality indicator:
a) RDS signal quality;
b) polarity difference and integral data.
– Selectable time constant for 57KHz PLL.
– Selectable inhibit of PLL regulation to be used for
AF tests and temporary field strength weakness
(i.e. tunnels or other obstacles to radio recep-
tion).
– Fast ARI indicator, controlled by software.
Figure 33. RDS Demodulator Block Diagram
0
1
0
1
0
1
RDSCOMP
arp aren
lock upr
qen
lck1 lck0
57KHz PLL
Fast ARI Indicator
“Polarity” Bi-phase
Decoder
“Integral” Bi-phase
Decoder
Differential
Decoder 1
dat1
Differential
Decoder 2
dat2
sdat
RDS Dat
qual2
Quality
Detector
qual1
lck3
lck2 squal
RDS Clock
QUALITY
1187.5Hz Bit PLL
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