參數(shù)資料
型號(hào)： ST62E30BF1
英文描述： MICROCONTROLLER|8-BIT|ST6200 CPU|CMOS|DIP|28PIN|CERAMIC
中文描述： 單片機(jī)| 8位| ST6200的CPU |的CMOS |雙酯| 28腳|陶瓷
文件頁(yè)數(shù)： 63/86頁(yè)
文件大?。?/td> 531K
代理商： ST62E30BF1
63/86
ST62T30B ST62E30B
REGISTERS
(Cont’d)
UART Control Register (UARTCR)
Address: D7h, Read/Write
Bit 7 =
RXRDY.
Receiver Ready. This flag be-
comes active as soon as a complete byte has
been received and copiedinto the receive buffer. It
may be cleared by writing a zero to it. Writing a
one is possible. If the interrupt enable bit RXIEN is
set to one, a software interrupt will be generated.
Bit 6 =
TXMT.
Transmitter Empty This flag be-
comes active as soon as a complete byte has
been sent. It maybe cleared by writing a zero to it.
It isautomatically cleared by the action of writing a
data value into the UART data register.
Bit 5 =
RXIEN.
Receive Interrupt Enable. When
this bit is set to 1, the receive interrupt is enabled.
Writing to RXIEN does not affect the status of the
interrupt flag RXRDY.
Bit 4 =
TXIEN.
Transmit Interrupt Enable When
this bit is set to 1, the transmitinterrupt is enabled.
Writing to TXIEN does not affect the status of the
interrupt flag TXRDY.
Bit 3-1=
BR2..BR0
. Baudrate select These bits
select the operating baud rate of the UART, de-
pending onthe frequency of fOSC. Care should be
taken not to change these bits during communica-
tion as writing to these bits has an immediate ef-
fect.
Bit 0 =
DAT9
. Parity/Data Bit 9 Thisbit represents
the 9th bit of the data character that is received or
transmitted. A write to this bit sets the level for the
bit 9 to be transmitted, so it must always be set to
the correct level before transmission. If used as
parity, the value has first to be calculated by soft-
ware. Reading this bit will return the 9th bit of the
received character.
7
0
RXRDY TXMT RXIEN TXIEN
BR2
BR1
BR0
DAT9
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