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參數(shù)資料
| 型號(hào)： | ST62E30BF1 |
| 英文描述： | MICROCONTROLLER|8-BIT|ST6200 CPU|CMOS|DIP|28PIN|CERAMIC |
| 中文描述： | 單片機(jī)| 8位| ST6200的CPU |的CMOS |雙酯| 28腳|陶瓷 |
| 文件頁(yè)數(shù)： | 51/86頁(yè) |
| 文件大?。?/td> | 531K |
| 代理商： | ST62E30BF1 |
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ST62T30B ST62E30B
5.2.3 TIMINGS MEASUREMENT MODES
These modes are based on the capture of the
down counter content into either CP or RLCP reg-
isters. Some are used in conjunction with a syn-
chronisation of the down counter by reload func-
tions on external event on CPi pins or software
RUNRES setting, while other modes do not affect
the downcounting. As long as RELOAD bit is
cleared, the down counter remains in free running
mode.
5.2.3.1
control
Three startup conditions, selected by RLDSELi bit
can reload the counter from RLCP and initiate the
down counting when RELOAD bit is set. The first
mode is software controlled through the RUNRES
bit, whilethetwo othersarebased onexternalevent
on pins CP1 and CP2 with configurable polarities.
External event on CP2 pin (with configurable po-
larities) is used as strobe to launch the capture of
the CT counter into CP. When RELOAD bit is set,
RLCP cannotbe usedfor capture, since it contains
the reload value..
Finally, 3 different Reload/Capture sequences are
available:
Timing
measurement
with
startup
– CP1 triggered restart mode with CP2 event de-
tection.
– CP2 triggered restart mode with second CP2
event detection.
– Software triggered restart mode with CP2 event
detection.
CP1 triggered restart mode with CP2 event de-
tection
.
This mode is enabled for RLDSEL2=0 and
RLDSEL1=1.
External eventson CPipins areenabledassoon as
RUNRES bitis set, whichlets the prescaler andthe
down counterrunning. ThenextactiveedgeonCP1
causes the counter to be loaded from RLCP, the
CP1FLGtobe setandthedowncountingstartsfrom
RLCPvalue.EachfollowingactiveedgeonCP1 will
causeareloadofthecounter.IfCP1FLGisnotreset
beforethenextreload,theCP1ERRflagissetatthe
same time as the counter is reloaded. Both flags
should then be cleared by software.
While the counter is counting, any active edge on
CP2 will capturethe value of thecounter at that in-
stant into the CP Register and setthe CP2FLG bit.
If CP2FLG is not cleared before the following CP2
event, the CP2ERRflag bit is set, and no new cap-
ture can be performed
Capturing is re-enabled by clearing both CP2FLG
and CP2ERR.
If acaptureonCP2and areloadonCP1occuratthe
sametime,thecaptureof thecounterto CPismade
first, and then thecounterisreloaded fromRLCP.
Figure 29. CP1 Triggered Restart Mode with CP2 Event Detection
RELOAD
1
0
Reload on CP1,CP2, RUNRES /Capture CP2
Capture CP1 / Capture CP2
VR02007
COUNTER
CT
CP1
Set CP1FLG
Set CP1ERR
0000h
0000h
Disabled
Enable the Inputs
RUNRES
Software Reset
Reload and Start
Reload
Reload
Set CP1FLG
Disabled
Set CP2ERR
Disabled
Capture CT into CP
Set CP2FLG
CP2
Disabled
First Capture in CP
Then Reload
Set CP1ERR, CP2FLG
Clear all Flags
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