參數(shù)資料
型號： ST62E30BF1
英文描述： MICROCONTROLLER|8-BIT|ST6200 CPU|CMOS|DIP|28PIN|CERAMIC
中文描述： 單片機| 8位| ST6200的CPU |的CMOS |雙酯| 28腳|陶瓷
文件頁數(shù)： 55/86頁
文件大?。?/td> 531K
代理商： ST62E30BF1
55/86
ST62T30B ST62E30B
CONTROL REGISTERS
(Cont’d)
Status Control Register 3 (SCR3)
Address: E2h - Read/Write/Clear only
Bit 7 =
CP2POL
. CP2 Edge Polarity Select
CP2POL defines the polarity for triggering theCP2
event.
A 0 defines theaction on a falling edge on the CP2
input, a 1 on a rising edge.
Bit 6 =
CP2IEN
. CP2 Interrupt Enable. The Cap-
ture 2 Interrupt is masked when this bit is 0. Set-
ting the bit to 1 enables the CP2 event flag
CP2FLG to set the ARTIMER interrupt.
Bit 5 =
CP2FLG
. CP2 Interrupt Flag When this bit
is 0, no CP2 event has occurred since the last
clear of this flag. If the bit is at 1, the first CP2
event and capture into CP has occurred.
This bit cannot be set by program, only cleared.
Bit 4 =
CMPIEN
. Compare Int. Enable The Com-
pare Interrupt is masked when this bit is 0.
Setting the bit to 1 enables the Compare flag
CMPFLG to set the ARTIMER interrupt.
Bit 3 =
CMPFLG
. Compare Flag When this bit is
0, no Masked-Compare True event has occurred
since the last clear of this flag. If the bit is at 1, a
Masked-Compare event has occurred.
This bit cannot be set by program, only cleared.
Bit 2 =
ZEROIEN
. Compare to Zero Int Enable.
The Masked-Counter Zero Interrupt is masked
when this bit is 0. Setting the bit to 1 enables the
ZEROFLG flag to set the ARTIMER interrupt.
Bit 1 =
ZEROFLG
. Compare to Zero Flag When
this bit is 0, no Masked-Counter Zero event has
occurred since the last clear of this flag. If the bit is
at 1, a Masked-Counter Zero event has occurred
as the Masked Counter state equals 0 when run-
ning or on hold (not on Reset).
Bit 0 =
PWMMD
. PWM Output Mode Control The
PWM Output mode is set by this bit; when 0, the
PWM output is run in set/reset mode (the PWM
output is set on a Masked-Counter Zero event and
is reset when on a Masked-Compare event).
When 1 the PWM output is in toggle mode; PWM
toggles its state on every Masked-Compare event.
Notes
:
A Masked-Compareis the logicalAND ofthe Mask
Register MASK with the Counter Register CT,
compared with the logical AND of the compare
Register CMP: [(MASK & CT) = (MASK&CMP)].
A Masked-Counter Zero is the logical AND of the
Mask Register MASK with the Counter Register
CT, compared with zero: [(MASK & CT) = 0000h]
7
0
CP2POL
CP2IEN CP2FLG CMPIEN
CMFLG
ZEROIEN ZEROFLG PWMMD
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