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參數(shù)資料
| 型號(hào)： | ST62E30BF1 |
| 英文描述： | MICROCONTROLLER|8-BIT|ST6200 CPU|CMOS|DIP|28PIN|CERAMIC |
| 中文描述： | 單片機(jī)| 8位| ST6200的CPU |的CMOS |雙酯| 28腳|陶瓷 |
| 文件頁(yè)數(shù)： | 62/86頁(yè) |
| 文件大小： | 531K |
| 代理商： | ST62E30BF1 |
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ST62T30B ST62E30B
5.4.4 DATA RECEPTION
The UARTcontinuously looks for a falling edge on
the input pin whenever a transmission is not ac-
tive. Once an edge is detected it waits 1 bit time (8
states) to accommodate the Start bit, and then as-
sembles the following serial data stream into the
data register. The data in the ninth bit position is
copied into Bit 9, replacing any previous value set
for transmission. After all 9 bits have been re-
ceived, the Receiver waits for the duration of one
bit (forthe Stop bit) and then transfersthe received
data into the buffer register, allowing a following
character to be received. The interrupt flag
RXRDY is setto 1 as the data is transferred to the
buffer register and, if enabled, will generate an in-
terrupt.
If a transmission is started during the course of a
reception, the transmission takes priority and the
reception is stopped to free the resources for the
transmission. Thisimplies that a handshaking sys-
tem must be implemented, as polling of the UART
to detect reception is not available.
Figure 37. UART Data Output
5.4.5 INTERRUPT CAPABILITIES
Both reception and transmission processes can in-
duce interrupt to the core as defined in the inter-
rupt section. These interrupts are enabled by set-
ting TXIEN and RXIEN bit in the UARTCR register,
and TXMT and RXRDY flags are set accordingly
to the interrupt source.
5.4.6 REGISTERS
UART Data Register (UARTDR)
Address: D6h, Read/Write
Bit7-Bit0. UART data bits A write to this register
loads the data into the transmit shift register and
triggers the start of transmission. In addition this
resets the transmit interrupt flag TXMT. A read of
this register returns the data from the Receive
buffer.
Warning
. No Read/Write Instructions may be
used with this registeras both transmit and receive
share the same address
Table 20. Baud Rate Selection
TXD1
TXD
PORT DATA
OUTPUT
0
MUX
1
UARTOE
VR02011
7
0
D7
D6
D5
D4
D3
D2
D1
D0
BR2
BR2
BR0
f
INT
Division
Baud Rate
f
INT
= 8MHz
1200
2400
4800
9600
19200
31200
38400
Reserved
f
INT
= 4MHz
600
1200
2400
4800
9600
15600
19200
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6.656
3.328
1.664
832
416
256
208
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