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參數(shù)資料
| 型號(hào)： | ST62E30BF1 |
| 英文描述： | MICROCONTROLLER|8-BIT|ST6200 CPU|CMOS|DIP|28PIN|CERAMIC |
| 中文描述： | 單片機(jī)| 8位| ST6200的CPU |的CMOS |雙酯| 28腳|陶瓷 |
| 文件頁(yè)數(shù)： | 25/86頁(yè) |
| 文件大小： | 531K |
| 代理商： | ST62E30BF1 |
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ST62T30B ST62E30B
3.3 DIGITAL WATCHDOG
The digital Watchdog consists of a reloadable
downcounter timer which can be used to provide
controlled recovery from software upsets.
The Watchdog circuit generates a Resetwhen the
downcounter reaches zero. User software can
prevent this reset by reloading the counter, and
should therefore be written so that the counter is
regularly reloaded while the user program runs
correctly. Inthe event of a software mishap (usual-
ly caused by externally generated interference),
the user program will no longer behave in its usual
fashion and the timer register will thus not be re-
loaded periodically. Consequently the timer will
decrement down to 00h and reset the MCU. In or-
der to maximise the effectiveness of the Watchdog
function, user software must be written with this
concept in mind.
Watchdog behaviour is governed by two options,
known
as
“WATCHDOG
HARDWARE or SOFTWARE) and “EXTERNAL
STOP MODE CONTROL” (see Table 8).
In the SOFTWARE option, the Watchdog is disa-
bled until bit C of the DWDR registerhas been set.
ACTIVATION”
(i.e.
When the Watchdog is disabled, low power Stop
mode is available. Once activated, the Watchdog
cannot be disabled, except by resetting the MCU.
In the HARDWARE option, the Watchdog is per-
manently enabled. Sincethe oscillator will run con-
tinuously, low power mode is not available. The
STOP instruction is interpreted as a WAIT instruc-
tion, and the Watchdog continues to countdown.
However, when the EXTERNAL STOP MODE
CONTROL option has been selected low power
consumption may be achieved in Stop Mode.
Execution of the STOP instruction is then gov-
erned by a secondary function associated with the
NMI pin. If a STOP instruction is encountered
when the NMI pin is low, it is interpreted as WAIT,
as described above. If, however, the STOP in-
struction is encountered when the NMI pin is high,
the Watchdog counter is frozen and the CPU en-
ters STOP mode.
When the MCU exits STOP mode(i.e. when anin-
terrupt is generated), the Watchdog resumes its
activity.
Table 8. Recommended Option Choices
Functions Required
Stop Mode & Watchdog
Stop Mode
Watchdog
Recommended Options
“EXTERNAL STOP MODE” & “HARDWARE WATCHDOG”
“SOFTWARE WATCHDOG”
“HARDWARE WATCHDOG”
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