參數(shù)資料
型號： ST62E30BF1
英文描述： MICROCONTROLLER|8-BIT|ST6200 CPU|CMOS|DIP|28PIN|CERAMIC
中文描述： 單片機| 8位| ST6200的CPU |的CMOS |雙酯| 28腳|陶瓷
文件頁數(shù)： 31/86頁
文件大小： 531K
代理商： ST62E30BF1
31/86
ST62T30B ST62E30B
INTERRUPTS
(Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable theindividual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h
—
Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused.
Bit 6 =
LES
: Level/Edge Selection bit
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 =
ESB
: Edge Selection bit
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4=
GEN
: Global Enable Interrupt When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive butcannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
7
0
-
LES
ESB
GEN
-
-
-
-
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