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參數(shù)資料
| 型號(hào)： | ST62E30BF1 |
| 英文描述： | MICROCONTROLLER|8-BIT|ST6200 CPU|CMOS|DIP|28PIN|CERAMIC |
| 中文描述： | 單片機(jī)| 8位| ST6200的CPU |的CMOS |雙酯| 28腳|陶瓷 |
| 文件頁數(shù)： | 44/86頁 |
| 文件大?。?/td> | 531K |
| 代理商： | ST62E30BF1 |
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ST62T30B ST62E30B
5.1 TIMER
The MCU features an on-chip Timer peripheral,
consisting of an 8-bit counter with a 7-bit program-
mable prescaler, giving a maximum count of 2
15
.
The peripheralmay be configuredin three different
operating modes.
Figure 24 shows the Timer Block Diagram. The
external TIMER pin is available to the user. The
content of the 8-bit counter can be read/written in
the Timer/Counterregister, TCR, while the state of
the 7-bit prescaler can beread inthe PSC register.
The control logic device is managed in the TSCR
register as described in the following paragraphs.
The 8-bit counter is decremented by the output
(rising edge) coming from the 7-bit prescaler and
can be loaded and read under program control.
When it decrements to zero then the TMZ (Timer
Zero) bit in the TSCR is set to “1”. If the ETI (Ena-
ble Timer Interrupt) bit in the TSCR is also set to
“1”, an interrupt request is generated as described
in the Interrupt Chapter. The Timer interrupt can
be used to exit the MCU from WAIT mode.
The prescaler input can be the internal frequency
f
INT
divided by 12 or an external clock applied to
the TIMER pin. The prescaler decrements on the
rising edge. Depending on the division factor pro-
grammed by PS2, PS1 and PS0 bits in the TSCR.
The clock input of the timer/counter register is mul-
tiplexed to different sources. For division factor 1,
the clock input of the prescaler is also that of tim-
er/counter; for factor 2, bit 0 of the prescaler regis-
ter is connected to the clock input of TCR. This bit
changes its state at half the frequency of the pres-
caler input clock. For factor 4, bit 1 of the PSC is
connected to the clock input of TCR, and so forth.
The prescaler initialize bit, PSI, in the TSCR regis-
ter must be set to “1” to allow the prescaler (and
hence the counter) to start. If it is cleared to “0”, all
the prescaler bits are set to “1” and the counter is
inhibited from counting. The prescaler can be
loaded with any value between 0 and 7Fh, if bit
PSI is set to “1”. The prescaler tap is selected by
means of the PS2/PS1/PS0 bits in the control reg-
ister.
Figure 25 illustrates the Timer’s working principle.
Figure 24. Timer Block Diagram
DATABUS 8
8
8
8
8-BIT
COUNTER
6
5
4
3
2
1
0
PSC
STATUS/CONTROL
REGISTER
TOUT
DOUT
b7
b6
b5
b4
b3
b2
b1
b0
TMZ
ETI
PSI
PS2
PS1
PS0
SELECT
1 OF7
3
LATCH
SYNCHRONIZATION
LOGIC
TIMER
INTERRUPT
LINE
VA00009
:12
f
OSC
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