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參數(shù)資料
| 型號： | SII3512ECTU128 |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP128 |
| 封裝： | LEAD FREE, TQFP-128 |
| 文件頁數(shù)： | 91/132頁 |
| 文件大?。?/td> | 3011K |
| 代理商： | SII3512ECTU128 |
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SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
DS-0102-D01
2007-2010 Silicon Image, Inc. All rights reserved.
53
CONFIDENTIAL
Bit [03]: PBM Rd-Wr (R/W) – PCI Bus Master Read-Write Control. This bit is set to specify a DMA write
operation from IDE1 to system memory. This bit is cleared to specify a DMA read operation from system memory
to an IDE1 device.
Bit [02:01]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [00]: PBM Enable (R/W) – PCI Bus Master Enable – IDE1. This bit is set to enable PCI bus master
operations for IDE Channel #1. PCI bus master operations can be halted by clearing this bit, but will erase all state
information in the control logic. If this bit is cleared while the PCI bus master is active, the operation will be
aborted and the data discarded. While this bit is set, accessing IDE1 Task File or PIO data registers will be
terminated with Target-Abort.
PRD Table Address – IDE1
Address Offset: 0x0C
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address – IDE1
Re
se
rve
d
This register defines the PRD Table Address register for IDE Channel #1 in the SiI3512 controller. The register bits are
defined below.
Bit [31:02]: PRD Table Address (R/W) – Physical Region Descriptor Table Address. This bit field defines the
Descriptor Table base address.
Bit [01:00]: Reserved (R). This bit field is reserved and returns zeros on a read.
PCI Bus Master2 – IDE0
Address Offset: 0x10
Access Type: Read/Write
Reset Value: 0x0808_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE
1
P
B
M
S
im
p
lex
IDE
1
P
B
M
DM
A
Cap
0
IDE
1
P
B
M
DM
A
Cap
1
IDE
1
Wat
ch
d
og
IDE
1
B
u
ff
er
E
m
p
ty
IDE
1
DM
A
Com
p
IDE
1
P
B
M
E
rr
or
IDE
1
P
B
M
Ac
tive
IDE
0
P
B
M
S
im
p
lex
IDE
0
P
B
M
DM
A
Cap
1
IDE
0
P
B
M
DM
A
Cap
0
IDE
0
Wat
ch
d
og
IDE
0
B
u
ff
er
E
m
p
ty
IDE
0
DM
A
Com
p
IDE
0
P
B
M
E
rr
or
IDE
0
P
B
M
Ac
tive
IDE
Wat
ch
d
og
IDE
1
DM
A
Com
p
Software
Re
se
rve
d
S
AT
AI
NT
1
Re
se
rve
d
S
AT
AI
NT
0
P
B
M
Rd
-Wr
Re
se
rve
d
P
B
M
E
n
ab
le
This register defines the second PCI bus master register for IDE Channel #0 in the SiI3512 controller. The system must
access these register bits through this address to enable the Large Block Transfer Mode.
The register bits are defined below.
Bit [31:29]: (R) – These bits are copy of PCI Bus Master IDE1 bits [23:21].
Bit [28]: IDE1 Watchdog (R): This bit is a copy of bit 12 in IDE1 Task File Configuration + Status register.
Bit [27]: IDE1 Buffer empty (R). This bit set indicates the IDE1 FIFO is empty.
Bit [26:24]: (R) – These bits are copy of PCI Bus Master IDE1 bits [18:16].
Bit [23]: PBM Simplex (R) – PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to
indicate that both IDE channels can operate as PCI bus master at any time.
Bit [22]: PBM DMA Cap 1 (R/W) – PCI Bus Master DMA Capable – Device 1. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [21]: PBM DMA Cap 0 (R/W) – PCI Bus Master DMA Capable – Device 0. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [20]: IDE0 Watchdog (R): This bit is a copy of bit 12 in IDE0 Task File Configuration + Status register.
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相關代理商/技術參數(shù) |
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|---|---|
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| SII3611 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SATALink Device Bridge |
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