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參數(shù)資料
| 型號(hào)： | SII3512ECTU128 |
| 元件分類(lèi)： | 總線(xiàn)控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP128 |
| 封裝： | LEAD FREE, TQFP-128 |
| 文件頁(yè)數(shù)： | 69/132頁(yè) |
| 文件大?。?/td> | 3011K |
| 代理商： | SII3512ECTU128 |
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SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
DS-0102-D01
2007-2010 Silicon Image, Inc. All rights reserved.
33
CONFIDENTIAL
Base Address Register 3
Address Offset: 0x1C
Access Type: Read/Write
Reset Value: 0x0000_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Base Address Register 3
Not
Used
This register defines the addressing of various control functions within the SiI3512 controller. The register bits are
defined below.
Bit [31:02]: Base Address Register 3 (R/W). This register defines the I/O Space base address for the IDE Channel
#1 Device Control- Alternate Status register.
Bit [01:00]: Base Address Register 3 (R). This bit field is not used and is hardwired to 0b01.
Base Address Register 4
Address Offset: 0x20
Access Type: Read/Write
Reset Value: 0x0000_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Base Address Register 4
Not Used
This register defines the addressing of various control functions within the SiI3512 controller. The register bits are
defined below.
Bit [31:04]: Base Address Register 4 (R/W). This register defines the I/O Space base address for the PCI bus
master registers.
Bit [03:00]: Base Address Register 4 (R). This bit field is not used and is hardwired to 0b0001.
Base Address Register 5
Address Offset: 0x24
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Base Address Register 5
Not Used
This register defines the addressing of various control functions within the SiI3512 device. This register is enabled when
input BA5_EN is set to one (see description for pin FL_ADDR[01]/BA5_EN in Miscellaneous I/O Pins section on page
15. The register bits are defined below.
Bit [31:09]: Base Address Register 5 (R/W). This register defines the Memory Space base address for all Silicon
Image driver specific functions.
Bit [08:00]: Base Address Register 5 (R). This bit field is not used and is hardwired to 0x00.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SII3531ACNU | PCI BUS CONTROLLER, QCC48 |
| SIO10N268-NU | MULTIFUNCTION PERIPHERAL, PQFP128 |
| SIS300 | GRAPHICS PROCESSOR, PBGA365 |
| SK12430PJT | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| SK12439PJ | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SII3531 | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:SteelVine⑩ Host Controller |
| SII3531A | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:PCI Express to Serial ATA Controller |
| SII3531ACNU | 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 48-Pin QFN EP |
| SII3611 | 制造商:SILICONIMAGE 制造商全稱(chēng):SILICONIMAGE 功能描述:SATALink Device Bridge |
| SII3611CT80-1.5 | 制造商:SILICON IMAGE 功能描述:3611CT80-1.5 |
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