SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
DS-0102-D01
2007-2010 Silicon Image, Inc. All rights reserved.
117
CONFIDENTIAL
Reading and Writing of Task File and Device Control Registers
48-bit LBA Addressing
The
SiI3512 supports 48-bit LBA. The
SiI3512 does not differentiate a non-extended command (one that does not use
48-bit LBA address) from an extended command (one that uses the 48-bit LBA address). The "expanded" registers can be
read with the HOB bit of the Device Control register se to '1'.
Device Control Register and Soft Reset
When the Device Control register is written, a Register FIS for Control will be sent downstream upon one of the
following conditions:
There is a change in the SRST bit, or;
With SRST bit being '0', there is a change in the NIEN bit.
Note that:
When the SRST is '1', the NIEN bit in the Register FIS sent is insignificant.
Any change in the HOB bit will not initiate any Register FIS to be sent. In fact, HOB bit is always '0' in the
Register FIS sent.
If the Serial ATA channel is in PARTIAL or SLUMBER state, a COMWAKE will be automatically initiated to
wake up the channel before the Register FIS is sent. However, the channel will stay at the ON state at the end of
the operation, even if no soft reset occurs.
A soft reset will do the following:
Wake up the downstream Serial ATA device from ATA IDLE, STANDBY or SLEEP.
LED Support
The SiI3512 supports two activity LEDs via two 12-mA open-drain drivers, LED[0..1]. LED0 indicates activity in IDE
Channel 0 and LED1 indicates activity in IDE Channel 1.
When there is activity for a non-ATAPI device, as indicated by BSY in the ATA Status being set, or when any bit in the
Serial ATA SActive register is set, the corresponding LED driver outputs will be driven low.
There is no activity LED support for ATAPI device. If the downstream device is an ATAPI device, the corresponding
LED output will not be driven low.