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參數(shù)資料
| 型號(hào)： | SII3512ECTU128 |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP128 |
| 封裝： | LEAD FREE, TQFP-128 |
| 文件頁(yè)數(shù)： | 48/132頁(yè) |
| 文件大?。?/td> | 3011K |
| 代理商： | SII3512ECTU128 |
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SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
14
2007-2010 Silicon Image, Inc. All rights reserved.
DS-0102-D01
CONFIDENTIAL
PCI Device Select
Pin Name: PCI_DEVSEL_N
Pin Number: 101
Device Select, when actively driven, indicates the driving device has decoded its address as the target of the current
access. As an input, PCI_DEVSEL_N indicates to a master whether any device on the bus has been selected.
PCI Stop
Pin Name: PCI_STOP_N
Pin Number: 100
PCI_STOP_N indicates the current target is requesting that the master stop the current transaction.
PCI Parity Error
Pin Name: PCI_PERR_N
Pin Number: 99
PCI_PERR_N indicates a data parity error between the current master and target on PCI. On a write transaction, the
target always signals data parity errors back to the master on PCI_PERR_N. On a read transaction, the master asserts
PCI_PERR_N to indicate to the system that an error was detected.
PCI System Error
Pin Name: PCI_SERR_N
Pin Number: 103
System Error is for reporting address parity errors, data parity errors on Special Cycle Command, or any other system
error where the result will be catastrophic. The PCI_SERR_N is a pure open drain and is actively driven for a single PCI
clock by the agent reporting the error. The assertion of PCI_SERR_N is synchronous to the clock and meets the setup and
hold times of all bused signals. However, the restoring of PCI_SERR_N to the de-asserted state is accomplished by a
weak pull-up. Note that if an agent does not want a non-maskable interrupt (NMI) to be generated, a different reporting
mechanism is required.
PCI Parity
Pin Name: PCI_PAR
Pin Number: 104
PCI_PAR is even parity across PCI_AD[31:0] and PCI_CBE[3:0]_N. Parity generation is required by all PCI agents.
PCI_PAR is stable and valid one clock after the address phase. For data phases PCI_PAR is stable and valid one clock
after either PCI_IRDY_N is asserted on a write transaction or PCI_TRDY_N is asserted on a read transaction. Once
PCI_PAR is valid, it remains valid until one clock after the completion of the current data phase. (PCI_PAR has the same
timing as PCI_AD[31:0] but delayed by one clock.)
PCI Request
Pin Name: PCI_REQ_N
Pin Number: 71
This signal indicates to the arbiter that this agent desires use of the PCI bus.
PCI Grant
Pin Name: PCI_GNT_N
Pin Number: 70
This signal indicates to the agent that access to the PCI bus has been granted. In response to a PCI request, this is a point-
to-point signal. Every master has its own PCI_GNT_N, which must be ignored while PCI_RST_N is asserted.
PCI Interrupt A
Pin Name: PCI_INTA_N
Pin Number: 67
Interrupt A is used to request an interrupt on the PCI bus. PCI_INTA_N is open collector and is an open drain output.
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