參數(shù)資料
型號(hào): SII3512ECTU128
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PQFP128
封裝: LEAD FREE, TQFP-128
文件頁(yè)數(shù): 13/132頁(yè)
文件大小: 3011K
代理商: SII3512ECTU128
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SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
DS-0102-D01
2007-2010 Silicon Image, Inc. All rights reserved.
3
CONFIDENTIAL
Functional Block Diagram
Figure 1. SiI3512 Block Diagram
PCI Interface
The SiI3512 controller PCI interface is compliant with the PCI Local Bus Specification (Revision 2.3). The SiI3512
device can act as a PCI master and a PCI slave, and contains the SiI3512 controller PCI configuration space and internal
registers. When the SiI3512 needs to access shared memory, it becomes the bus master of the PCI bus and completes the
memory cycle without external intervention. In the mode when it acts as a bridge between the PCI bus and the Serial ATA
bus, it will behave as a PCI slave.
PCI Initialization
Generally, when a system initializes a module containing a PCI device, the configuration manager reads the configuration
space of each PCI device on the PCI bus. Hardware signals select a specific PCI device based on a bus number, a slot
number, and a function number. If a device that is addressed (via signal lines) responds to the configuration cycle by
claiming the bus, then that function's configuration space is read out from the device during the cycle. Because any PCI
device can be a multifunction device, every supported function's configuration space needs to be read from the device.
Based on the information read, the configuration manager will assign system resources to each supported function within
the device. Sometimes new information needs to be written into the function's configuration space. This is accomplished
with a configuration write cycle.
PCI Bus Operations
The SiI3512 controller behaves either as a PCI master or a PCI slave device at any time and switches between these
modes as required during device operation.
As a PCI slave, the SiI3512 controller responds to the following PCI bus operations:
I/O Read
I/O Write
Configuration Read
Configuration Write
Memory Read
Memory Write
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