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參數(shù)資料
| 型號： | SII3512ECTU128 |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP128 |
| 封裝： | LEAD FREE, TQFP-128 |
| 文件頁數(shù)： | 90/132頁 |
| 文件大?。?/td> | 3011K |
| 代理商： | SII3512ECTU128 |
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SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
52
2007-2010 Silicon Image, Inc. All rights reserved.
DS-0102-D01
CONFIDENTIAL
aborted and the data discarded. While this bit is set, accessing IDE0 Task File or PIO data registers will be
terminated with Target-Abort.
PRD Table Address – IDE0
Address Offset: 0x04
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address – IDE0
Re
se
rve
d
This register defines the PRD Table Address register for IDE Channel #0 in the SiI3512 controller. The register bits are
defined below.
Bit [31:02]: PRD Table Address (R/W) – Physical Region Descriptor Table Address. This bit field defines the
Descriptor Table base address.
Bit [01:00]: Reserved (R). This bit field is reserved and returns zeros on a read.
PCI Bus Master – IDE1
Address Offset: 0x08
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
P
B
M
S
im
p
lex
P
B
M
DM
A
Cap
1
P
B
M
DM
A
Cap
0
Re
se
rve
d
IDE
1
DM
A
Com
p
P
B
M
E
rr
or
P
B
M
Ac
tive
Reserved
P
B
M
Rd
-Wr
Re
se
rve
d
P
B
M
E
n
ab
le
This register defines the PCI bus master register for IDE Channel #1 in the SiI3512 controller. The register bits are
defined below.
Bit [31:24]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [23]: PBM Simplex (R) – PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to
indicate that both IDE channels can operate as PCI bus master at any time.
Bit [22]: PBM DMA Cap 1 (R/W) – PCI Bus Master DMA Capable – Device 1. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [21]: PBM DMA Cap 0 (R/W) – PCI Bus Master DMA Capable – Device 0. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [20:19]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [18]: IDE1 DMA Comp (R/W1C) – IDE1 DMA Completion Interrupt. During write DMA operation, this bit
set indicates that the IDE1 interrupt has been asserted and all data has been written to system memory. During
Read DMA, this bit set indicates that the IDE1 interrupt has been asserted. This bit must be W1C by software
when set during DMA operation (bit 0 is set). During normal operation, this bit reflects IDE1 interrupt line.
Bit [17]: PBM Error (R/W1C) – PCI Bus Master Error – IDE1. This bit set indicates that a PCI bus error
occurred while the SiI3512 controller was bus master. Additional information is available in the PCI Status
register in PCI Configuration space.
Bit [16]: PBM Active (R) – PCI Bus Master Active – IDE1. This bit set indicates that the SiI3512 controller is
currently active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data transfers
have completed or PBM Enable bit is not set.
Bit [15:08]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [07:04]: Reserved (R). This bit field is reserved and returns zeros on a read.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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| SII3611 | 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:SATALink Device Bridge |
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