參數(shù)資料
型號(hào)： SII3512ECTU128
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PQFP128
封裝： LEAD FREE, TQFP-128
文件頁數(shù)： 65/132頁
文件大?。?/td> 3011K
代理商： SII3512ECTU128
SiI3512 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
30
2007-2010 Silicon Image, Inc. All rights reserved.
DS-0102-D01
CONFIDENTIAL
PCI Status – PCI Command
Address Offset: 0x04
Access Type: Read/Write/Write-One-to-Clear
Reset Value: 0x02B0_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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This register defines the various control functions associated with the PCI bus. The register bits are defined below.
Bit 31: Det. Par Err (R/W1C) – Detected Parity Error. This bit set indicates that the SiI3512 device detected a
parity error on the PCI bus-address or data parity error-while responding as a PCI target.
Bit 30: Sig. Sys Err (R/W1C) – Signaled System Error. This bit set indicates that the SiI3512 controller signaled
SERR on the PCI bus.
Bit 29: Rcvd M Abort (R/W1C) – Received Master Abort. This bit set indicates that the SiI3512 controller
terminated a PCI bus operation with a Master Abort.
Bit 28: Rcvd T Abort (R/W1C) – Received Target Abort. This bit set indicates that the SiI3512 controller received
a Target Abort termination.
Bit 27: Sig. T Abort (R/W1C) – Signaled Target Abort. This bit set indicates that the SiI3512 controller
terminated a PCI bus operation with a Target Abort.
Bit [26:25]: Devsel Timing (R) – Device Select Timing. This bit field indicates the DEVSEL timing supported by
the SiI3512 device. The hardwired value is 0b01 for Medium decode timing.
Bit 24: Det M Data Par Err (R/W1C) – Detected Master Data Parity Error. This bit set indicates that the SiI3512
controller, as bus master, detected a parity error on the PCI bus. The parity error may be either reported by the
target device via PERR# on a write operation or by the SiI3512 controller on a read operation.
Bit 23: Fast B-to-B Capable (R) – Fast Back-to-Back Capable. This bit is hardwired to 1 to indicate that the
SiI3512 controller is Fast Back-to-Back capable as a PCI target.
Bit 22: Reserved (R).
Bit 21: 66-MHz Capable (R) – 66-MHz PCI Operation Capable. This bit is hardwired to 1 to indicate that the
SiI3512 device is 66-MHz capable.
Bit 20: Capabilities List (R) – PCI Capabilities List. This bit is hardwired to 1 to indicate that the SiI3512
controller has a PCI Power Management Capabilities register linked at offset 0x34.
Bit 19: Interrupt Status (R).
Bit [18:11]: Reserved (R) – This bit field is reserved and returns zeros on a read.
Bit 10: Interrupt Disable (R/W)
Bit 09: Fast B-to-B Enable (R) – Fast Back-to-Back Enable. This bit is hardwired to 0 to indicate that the SiI3512
controller does not support Fast Back-to-Back operations as bus master.
Bit 08: SERR Enable (R/W) – SERR Output Enable. This bit set enables the SiI3512 controller to drive the PCI
SERR# pin when it detects an address parity error. The Parity Error Response bit (06) must also be set to enable
SERR# reporting.
Bit 07: Address Stepping (R) – Address Stepping Enable. This bit is hardwired to 0 to indicate that the SiI3512
controller does not support Address Stepping.
Bit 06: Par Error Response (R/W) – Parity Error Response Enable. This bit set enables the SiI3512 controller to
respond to parity errors on the PCI bus. If this bit is cleared, the SiI3512 controller will ignore PCI parity errors.
Bit 05: VGA Palette (R) – VGA Palette Snoop Enable. This bit is hardwired to 0 to indicate that the SiI3512
controller does not support VGA Palette Snooping.
Bit 04: Mem Wr & Inv (R) – Memory Write and Invalidate Enable. This bit is hardwired to 0 to indicate that the
SiI3512 device does not support Memory Write and Invalidate.
Bit 03: Special Cycles (R) – Special Cycles Enable. This bit is hardwired to 0 to indicate that the SiI3512
controller does not respond to Special Cycles.
Bit 02: Bus Master (R/W) – Bus Master Enable. This bit set enables the SiI3512 device to act as PCI bus master.
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