- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383804 > SCANPSC110FSC (FAIRCHILD SEMICONDUCTOR CORP) SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) PDF資料下載
參數(shù)資料
| 型號： | SCANPSC110FSC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, MS-013, SOIC-28 |
| 文件頁數(shù)： | 24/25頁 |
| 文件大?。?/td> | 283K |
| 代理商： | SCANPSC110FSC |
www.fairchildsemi.com
24
S
9. After testing the interconnect on the individual boards,
the next step is to test the backplane interconnect. This
is a pair-wise test between Board #1 and each of the
other boards. Board #1 drives test patterns onto the
backplane wiring, and the currently addressed slave
board senses the written data via its backplane scan
interface. In this example, the interconnect between
Board #1 and Board #2 is tested first. To test this inter-
connect, the 1149.1-compliant backplane transceivers,
SCAN182245A, SCAN ABT Test Access Logic, on
each board must be accessed for scan operations (see
Figure 19). For more information on SCAN ABT live
insertion capabilities, refer to the SCAN182245A
datasheet.
First, the system master (Board #1) is addressed and
selected. The 1149.1-compliant SCAN ABT transceiv-
ers reside on the chain connected to LSP
2
on Board
#1. The mode register is re-configured so that only port
LSP
2
is in the chain, and the
UNPARK
instruction is
then used to access this chain. The appropriate
instruction register and data register scan sequencing
is then performed to apply a pattern to the backplane
using the SCAN ABT bus transceiver.
10. To test the backplane interconnect, LSP
2
of Board #1
must be parked in the
Run-Test/Idle
TAP controller
state, so that the EXTEST command will stay active
when Board #1 is de-selected (the
PARKRTI
instruc-
tion is issued). The
GOTOWAIT
instruction is then
issued to return all boards to the
Wait-For-Address
state. Each one of the slave boards is then addressed,
one at a time, to sample the backplane signals being
driven by Board #1. For example, Board #2 is
addressed. The mode register is reconfigured, (if
needed), to select the scan chain (LSP
2
) that includes
the SCAN ABT backplane transceivers for Board #2.
The
UNPARK
instruction is issued to unpark LSP
n
and
insert it into the active scan chain. The
SAMPLE/PRE-
LOAD
instruction is issued to the SCAN ABT back-
plane transceivers, (
BYPASS
to other components in
the scan chain). The backplane is sampled by
sequencing the TAP controller through the
Capture-DR
state and the data is shifted out and checked by the
tester. The
PARKRTI
instruction is then given to park
LSP
n
of Board #2 in the
Run-Test/Idle
state, and the
GOTOWAIT
instruction is issued to return all
SCANPSC110Fs to the
Wait-For-Address
state so that
the next board, (Board #3), can be sampled. This pro-
cedure is repeated for boards #3
–
#8, then Board #1 is
selected again, a new pattern is shifted out and driven
by the
EXTEST
command, and the slave boards are
again sampled.
11. Step 10 is repeated until the backplane interconnect
has been sufficiently tested.
12. When testing is complete, the controller sends out the
SOFTRESET
instruction to all SCANPSC110Fs. This is
accomplished by first using the broadcast address,
“
3B
”
Hex, to select all SCANPSC110Fs. The
SOFTRE-
SET
command is then loaded, causing TMS
L(1
–
3)
sig-
nals to go HIGH; this drives all local TAPs into the
Test-
Logic-Reset
state within five TCK cycles.
FIGURE 19. Testing the Backplane Interconnections
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SCP-5453 | SOCKET,IC,16PIN,MACHINE TOOLED WIRE WRAP,0.3"WIDE,0.515"LEAD |
| SCP-6122 | POWER OPERATIONAL AMPLIFIER |
| SCS152 | HM Series Hermetically Sealed Basic Switch, Single Pole Double Throw Circuitry, 0.5 A at 28 Vdc, Integral Lever Actuator, Solder Termination |
| SCS152-IS | Small glass bead with axial leads |
| SCS152-IW | Small glass bead with axial leads |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCANPSC110FSCX | 功能描述:特定功能邏輯 SCAN JTAG Port RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SCANSTA101 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage IEEE 1149.1 STA Master |
| SCANSTA101_06 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage IEEE 1149.1 STA Master |
| SCANSTA101SM | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANSTA101SM/NOPB | 功能描述:接口 - 專用 Low Vltg IEEE 1149.1 Sys Test Access RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。