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參數(shù)資料
| 型號： | SCANPSC110FSC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, MS-013, SOIC-28 |
| 文件頁數(shù)： | 23/25頁 |
| 文件大小： | 283K |
| 代理商： | SCANPSC110FSC |
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www.fairchildsemi.com
S
Each target slot address is addressed by first sequenc-
ing all SCANPSC110Fs on the backplane to the
Shift-
IR
state, and then by shifting in the address of the tar-
get slot. The SCANPSC110F TAP controller is then
sequenced through the Update-IR state. If a
SCANPSC110F with the matching slot identification is
present, it is selected. All other SCANPSC110Fs are
unselected. To determine whether that slot contains a
selected SCANPSC110F, the tester must read back the
SCANPSC110Fs S
0
–
5
value (if present).
The tester moves the selected SCANPSC110F from
the
Update-IR
state back to the
Shift-IR
state, and the
instruction register is then scanned while loading the
next instruction
(GOTOWAIT)
. During the
Capture-IR
state of the TAP Controller, a
“
01
”
pattern is loaded into
the two least significant bits of the SCANPSC110F's
instruction register, and the most significant six bits
capture the value on the S
0
–
5
pins. The captured data
is shifted out while the GOTOWAIT command is shifted
in. If an
“
all ones
”
pattern is returned, a board does not
exist at that location. (The
“
all ones
”
pattern is caused
by the pull-up resistor on the TDI input of the controller,
as required for 1149.1 compliance.)
At the end of instruction register scan, the
GOTOWAIT
command is issued and all SCANPSC110F selection
controllers enter the
Wait-For-Address
state. This
allows the next SCANPSC110F in the polling sequence
to be addressed. The polling process is repeated for
every possible board address in the system. In this
example, the tester finds that boards #1 through #8 are
present, and boards #9 and #10 are missing. There-
fore, it will report back its findings and will not attempt
to test the missing boards.
3. Infrastructure testing of the populated boards may now
proceed. The tester addresses the SCANPSC110F on
Board #1 for test operations. SCANPSC110F #1 is now
selected, while all others are unselected.
Board #1 is wired such that all LSP
n
's are connected to
individual scan chains. The first objective is to test the
scan chain integrity of the board. For this task, it is
more efficient to configure the LSPN such that all three
chains are placed in series. To accomplish this, the
MODESEL
instruction is issued to place the mode reg-
ister into the active scan chain, and the binary value
“
00000111
”
is shifted into the mode register. The
UNPARK
instruction is then issued to access all three
local chains.
Once the
UNPARK
instruction has been updated and
the SCANPSC110F TAP controller is synchronized with
the local TAP's, the scan chain integrity test can be per-
formed on the local scan chains. This test is done by
performing a
Capture-IR
and then shifting the scan
chain checking the 2 least significant bits of each com-
ponents instruction register for
“
01
”
. If the LSB's of any
component in the scan chain are not
“
01
”
, the test fails.
Diagnostic software can be used to narrow down the
cause of the failure. Next the device identification of
each component in the scan chain is checked. This is
done by issuing the
IDCODE
instruction to each com-
ponent in the scan chain. Components that do not sup-
port
IDCODE
will insert their bypass register into the
active scan chain.
After the IDCODE register scan, the
GOTOWAIT
instruction is issued to reset the local scan ports and
return the SCANPSC110F Selection controller to the
Wait-For-Address state. A sequence similar to step 3 is
repeated for each board in the system.
4. Next, the tester addresses Board #1 to perform inter-
connect testing. For this task, it is efficient to configure
the LSPN such that all three chains are placed in
series. Therefore, the Mode register should be pro-
grammed with the binary value
“
00000111
”
(this was
done in step 3 above and need not be repeated unless
a
Test-Logic-Reset
was performed since then). The
UNPARK
instruction is issued to access all three local
chains.
Once the
UNPARK
instruction has been loaded and
the SCANPSC110F is synchronized with the local
TAPs, normal 1149.1 scan operations may commence.
To test the interconnect on Board #1, an instruction
register scan sequence is performed and the
SAMPLE/
PRELOAD
instruction is loaded into the instruction reg-
ister of all target devices. The
BYPASS
instruction is
loaded into the instruction register of SCANPSC110F
#1. A data register scan is now performed to preload
the first test vector to be applied to the interconnect.
5. After the preload operation is performed, an instruction
register scan is used to load the
EXTEST
instruction
into all TAPs (
BYPASS
loaded into SCANPSC110F
#1). The appropriate sequencing is now performed to
apply patterns in order to test the interconnect on
Board #1.
6. Upon completion of the interconnect test on Board #1,
the local chains must be parked. The
PARKTLR
com-
mand is loaded into the instruction register, and the
TMS
Ln
outputs of the three local chains are forced
HIGH, sending the three local TAPs into the
Test-Logic-
Reset
state.
7. Now that the Board #1 interconnect has been tested,
the interconnect on the other boards in the system
must be checked. All SCANPSC110F are returned to
the
Wait-For-Address
state by issuing the
GOTOWAlT
instruction. Board #2 is addressed next, followed by the
rest of the boards in the system. A sequence similar to
steps 4 through 6 is used for each board.
8. Assume that boards #6, #7 and #8 are identical, so that
it is possible to test them simultaneously. The tester
first addresses Board #6. Next the
MCGRSEL
instruc-
tion is issued to place the Multi-Cast Group register into
the active scan chain, and the binary value
“
01
”
is
shifted into the MCGR. The
GOTOWAIT
instruction is
then issued returning all SCANPSC110F's to the
Wait-
For-Address
state. The MCGR for SCANPSC110F #7
and SCANPSC110F #8 are programmed the same as
Board #6. Next the Multi-Cast address
“
00111101
”
is
issued by the tester, which causes the SCANPSC110F
Selection controller of SCANPSC110F #6
–
#8 to enter
the
Selected-Multi-Cast
state. The
LFSRON
instruction
is then issued to enable the signature compaction cir-
cuitry on the selected SCANPSC110Fs. The
SAMPLE/
PRELOAD
and
EXTEST
instructions are then used to
test the interconnects, similar to steps 4 and 5 above.
When the test sequence is complete, the
GOTOWAIT
instruction is issued returning all SCANPSC110Fs to
the
Wait-For-Address state
. SCANPSC110Fs #6, #7,
and #8 are then addressed one at a time to read back
the test signature from the LFSR (the LFSR is read by
selecting it with the
LFSRSEL
instruction, then scan-
ning out its contents.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCANPSC110FSCX | 功能描述:特定功能邏輯 SCAN JTAG Port RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SCANSTA101 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage IEEE 1149.1 STA Master |
| SCANSTA101_06 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage IEEE 1149.1 STA Master |
| SCANSTA101SM | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANSTA101SM/NOPB | 功能描述:接口 - 專用 Low Vltg IEEE 1149.1 Sys Test Access RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
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