- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383804 > SCANPSC110FSC (FAIRCHILD SEMICONDUCTOR CORP) SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) PDF資料下載
參數(shù)資料
| 型號： | SCANPSC110FSC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, MS-013, SOIC-28 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 283K |
| 代理商： | SCANPSC110FSC |
15
www.fairchildsemi.com
S
Special Features
BIST SUPPORT
The sequence of instructions to run BIST testing on a
parked SCANPSC110F Bridge port is as follows:
1. Pre-load the Boundary register of the device under test
if needed.
2. Initialize the TCK counter to 00000000 Hex. Note that
the TCK counter is initialized to 00000000 Hex upon
Test-Logic-Reset
, so this step may not be necessary.
3. Issue the
CNTRON
instruction to the SCANPSC110F,
to enable the TCK counter.
4. Shift the
PARKRTI
instruction into the SCANPSC110F
instruction register and
BIST
instruction into the
instruction register of the device under test.
5. Issue the
CNTRSEL
instruction to the SCANPSC110F.
6. Load the TCK counter (Shift the 32-bit value represent-
ing the number of TCK
L
cycles needed to execute the
BIST operation into the TCK counter register).
7. Bit 7 of the Mode register can be scanned to check the
status of the TCK counter, (
MODESEL
instruction fol-
lowed by a
Shift-DR
). Bit 7 logic
“
0
”
means the counter
has not reached terminal count, logic
“
1
”
means that
the counter has reached terminal count and the BIST
operation has completed.
8. Execute the
CNTROFF
instruction.
9. Unpark the LSP and scan out the result of the BIST
operation (the
CNTROFF
instruction must be executed
before unparking the LSP).
The Self test will begin on the rising edge of TCK
B
following
the
Update-DR
TAP controller state.
RESET
Reset operations can be performed at three levels. The
highest level resets all SCANPSC110F registers and all of
the local scan chains of selected and unselected
SCANPSC110Fs. This
“
Level 1
”
reset is performed when-
ever the SCANPSC110F TAP Controller enters the
Test-
Logic-Reset
state.
Test-Logic-Reset
can be entered syn-
chronously by forcing TMS
B
high for at least five (5) TCK
B
pulses, or asynchronously by asserting the TRST pin. A
“
Level 1
”
reset forces all SCANPSC110Fs into the
Wait-
For-Address
state, parks all local scan chains in the
Test-
Logic-Reset
state, and initializes all SCANPSC110F regis-
ters.
TABLE 10. Reset Configurations for Registers
The
SOFTRESET
instruction is provided to perform a
“
Level 2
”
reset of all LSP's of selected SCANPSC110Fs.
SOFTRESET
forces all TMS
L
signals HIGH, placing the
corresponding local TAP Controllers in the
Test-Logic-
Reset
state within five (5) TCK
B
cycles.
The third level of reset is the resetting of individual local
ports. An individual LSP can be reset by parking the port in
the
Test-Logic-Reset
state via the
PARKTLR
instruction. To
reset an individual LSP that is parked in one of the other
parked states, the LSP must first be unparked via the
UNPARK
instruction.
PORT SYNCHRONIZATION
When a LSP is not being accessed, it is placed in one of
the four TAP Controller states:
Test-Logic-Reset, Run-Test/
Idle, Pause-DR,
or
Pause-IR.
The SCANPSC110F is able
to park a local chain by controlling the local Test Mode
Select outputs (TMS
L(1
–
3)
) (see Figure 4). TMS
Ln
is forced
high for parking in the
Test-Logic-Reset
state, and forced
LOW for parking in
Run-Test/Idle, Pause-IR,
or
Pause-DR
states. Local chain access is achieved by issuing the
UNPARK
instruction. The LSPs do not become unparked
until the SCANPSC110F TAP Controller is sequenced
through a specified synchronization state. Synchronization
occurs in the
Run-Test/Idle
state for LSPs parked in
Test-
Logic-Reset
or
Run-Test/Idle;
and in the
Pause-DR
or
Pause-IR
state for ports parked in
Pause-DR
or
Pause-IR,
respectively.
Figures 11, 12 show the waveforms for synchronization of
a local chain that was parked in the
Test-Logic-Reset
state.
Once the
UNPARK
instruction is received in the instruction
register, the LSPC forces TMS
L
LOW on the falling edge of
TCK
B
.
FIGURE 11. Local Scan Port Synchronization on Second Pass
Register
MCGR
Instruction
Mode
LFSR
32-Bit Counter
Bit Width
2
8
8
16
32
Initial Hex Value
0
AA (
IDCODE
Instruction)
01
0000
00000000
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SCP-5453 | SOCKET,IC,16PIN,MACHINE TOOLED WIRE WRAP,0.3"WIDE,0.515"LEAD |
| SCP-6122 | POWER OPERATIONAL AMPLIFIER |
| SCS152 | HM Series Hermetically Sealed Basic Switch, Single Pole Double Throw Circuitry, 0.5 A at 28 Vdc, Integral Lever Actuator, Solder Termination |
| SCS152-IS | Small glass bead with axial leads |
| SCS152-IW | Small glass bead with axial leads |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCANPSC110FSCX | 功能描述:特定功能邏輯 SCAN JTAG Port RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SCANSTA101 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage IEEE 1149.1 STA Master |
| SCANSTA101_06 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage IEEE 1149.1 STA Master |
| SCANSTA101SM | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| SCANSTA101SM/NOPB | 功能描述:接口 - 專用 Low Vltg IEEE 1149.1 Sys Test Access RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。